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ADS54J69: TI-JESD204-IP What will be the minimal deterministic latency achieved

kuldip nln
Prodigy 10 points
Part Number: ADS54J69

Tool/software:

Hi Ameet, 

     I would like to know the total minimum deterministic latency achieved using ADS54J69 ADC device and the TI JESD204 IP. I need to have latency from the instant the signal applied at the ADC input to the parallel sample available inside FPGA to be minimized for my target application.  

Thanks

Kuldip

  • 0
    TI__Intellectual 1720 points

    Hi Kuldip,

    It is difficult to pre compute a number this way. There are many components of a JESD link with varying delays. The best approach to quickly achieve deterministic latency is to measure the delay and add enough margin to the release buffer delay to cover all possible variations.

    If you are interested in the smallest latency value, the only approach will be to measure the delay over multiple link/power recycles over a sweep of operating conditions and add the smallest margin allowed on the worst case delay you measure. 

    The typical delay can be approximately 120ns-200ns, but again, that is based on the averages seen. 

    Regards,

    Ameet

  • 0 in reply to Ameet Bagwe
    Prodigy 10 points

    Hi Ameet, 

        Thank you. is it possible for TI to benchmark this delay on the hardware? If the delay comes out to be 120ns or so, then I will be able to use this ADC device in my application.

    Thank you

    Kuldip

  • 0 in reply to kuldip nln
    TI__Intellectual 1720 points

    Hi Kuldip,

    Unfortunately, TI doesn’t benchmark this number because the delay will change with each LMFS mode, lane rate, FPGA PHY architecture and PHY deserialization mode. The delay can also change by another 1-2 core clock cycles based on the fifo synchronization architecture (as the elastic buffers are essentially clock domain crossing FIFOs).

    Due to these limitations, the TI JESD IP has been architected with hooks to easily measure Deterministic latency so customers can carry out the profiling on their setup.

    If you can let me know the LMFS mode and lane rate, I may be able to calculate a rough number, but the ideal way will be to set up the EVM with the FPGA devkit of your choice. 

    Regards,

    Ameet