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DAC38RF85: Search for a 100 MHz clock generator with 10 MHz reference

Alain Garot
Prodigy 50 points
Part Number: DAC38RF85
Other Parts Discussed in Thread: CDCE6214, LMK03318

Tool/software:

Hello,

I am studying a new design with DAC38RF85 chip (or other reference from the DAC38RF8x family).

The frequency reference of this design must be 10 MHz. This frequency is too low for the reference input of the DAC38RF85 (100 MHz min).

Thus, I am looking for a clock generator which will be able to generate a 100 MHz clock from the 10 MHz reference.

The phase noise at the output of the clock generator must comply with the following requirements (max values) : 

The aim is to get a cheap clock generator (< 5 $ for 500p) in a small package and with a low power consumption.

Since this clock generator will drive the DAC38RF8x part, one output shall be directly compatible. Another output (differential) will be required in order to supply the same 100 MHz reference to the processing part (output format to be defined).

What reference do you recommend for this kind of operation ?

Thanks for your help.

Regards,

Alain

  • 0
    TI__Genius 14250 points

    Alain,

    We may be able to support this phase noise requirement with the CDCE6214. I can check the result on a PNA and let you know by Monday.

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 50 points

    Hi Kadeem,

    Thanks for the information.

    If you can check the phase noise with the CDCE6214, it would be perfect !

    I am waiting for this result.

    Regards,

    Alain

  • 0 in reply to Alain Garot
    TI__Genius 14250 points

    Alain,

    Close-in phase noise will heavily depend on the performance of the 10MHz reference clock. The reference input may also partially contribute to the spurs. See below as an example of this:

    In this example, the input is a 25MHz XTAL rather than a 10MHz LVCMOS clock:

    Where does the phase noise requirement come from? I do not see anything about this listed in the datasheet for the DAC38RF85 device.

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 50 points

    Hi Kadeem,

    Thanks for these measurements.

    As you mentioned, the close-in phase noise depends on the phase noise of the 10 MHz reference.

    Do you have phase noise of the reference used for the first measurement ?

    Or, are you able to simulate the phase noise results using a 10 reference with the following phase noise ?

    -95 dBc/Hz @ 1 Hz

    -115 dBc/Hz @ 10 Hz

    -145 dBc/Hz @ 100 Hz

    -155 dBc/Hz @ 1 kHz

    To answer to your last question, the phase noise requirement comes from our needs for the generated signals at the output of the DAC according to the DVB standard. It is not a requirement of the DAC chip itself.

    Thanks,

    Alain

  • 0 in reply to Alain Garot
    TI__Genius 14250 points

    Alain,

    I used another CDCE6214 as the input (and that CDCE6214 was sourced by an XTAL) - I can provide this capture tomorrow.

    As for the phase noise simulation, I input the settings for the CDCE6214 into PLLatinum SIM with a noise-less reference and get the following results:

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 50 points

    Hi Kadeem,

    This simulation graph seems to show that the total phase noise is only due to the PLL, more particularly below 1 KHz. The phase noise of the reference is not displayed on this graph, difficult to know if the close-in phase noise is due to the PLL or the reference but the close-in phase noise slope (about 10 dB/decade) does not seem to be the one of a 10 MHz reference...

    Thus, if this phase noise is really due to the PLL, it means that this part will not be the good one in order to comply with the phase noise needs.

    Alain

  • 0 in reply to Alain Garot
    Prodigy 50 points

    Kadeem,

    There is the part LMK03318 which may fit to the needs.

    What do you think about that ?

    Are you able to have simulation or measurement results for phase noise validation at 100 MHz output ?

    Thanks,

    Alain

  • 0 in reply to Alain Garot
    TI__Intellectual 2685 points

    Alain,

    We will get back to you tomorrow with the phase noise validation.

    Best,

    Cris

  • 0 in reply to Cris Kobierowski
    TI__Genius 14250 points

    Alain,

    With an XTAL input, I get the following result on an LMK03318:

    For reference, this is what we observe when configuring an output as a buffered copy of the XTAL input:

    And this is the output that I get from PLLatinum Sim when I use a similar-performance reference as the input OSC:

    PLLatinum SIM is largely close to what we are seeing on the evaluation module.

    Now, if I use the parameters of your OSC as the input, this is what I see in PLLatinum SIM:

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 50 points

    Hello Kadeem,

    Thanks for these simulation results. It confirms that the LMK03318 is a good candidate, about phase noise, for this kind of application.

    Next step will be to check all the other features (mainly interfaces compatibility).

    Regards,

    Alain