Tool/software:
We want to use the ADC3241IRGZT in a new system. In addition to a differential CLK input , this also has a differential SYSREF input.
For this SYSREF, the data sheet only states that it is used for overall system synchronization. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization.”
But what does that look like? There is no timing diagram in the data sheet showing how the SYSREF works. Only table 7.13 contains values. SYSREF and INPUT-CLK seem to play together somehow.
Can you obtain more information, e.g. a timing diagram?
ciao
Hanno (on behalf of my customer)
