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TLV2548: TLV2548CPW

Part Number: TLV2548

Tool/software:

I have met a TLV2548CPW SPI boud rate issue , when I use SPI boud rate of 8M and read a channel with 40 periods , the AIN0-AIN2  digital output are all high level and result is wrong ,I have got a failure rate of 40 persents(8 out of 20), but when I decrease boud rate to 4M and the result is correct , I checked SCLK/SDI/SDO signal , they all looks great .see below Oscilloscope snapshoot , Could you please help to check why the chip cannot support 8M boud rate with the sample rate is200 kbps(=1*8M/40=200K/s) while OK to 4M boud rate? the datasheet  does specified the sample rate to be 200kbps.

8 M SPI boudrate: 

4M  SPI boud rate:

  • Hi Hong,

    Can you tell me what data you are expecting in and out of the ADC during this time? Is it the SDO data that is wrong during this time? Could I also see what the input to your ADC circuit looks like?

    Regards,
    Joel

  • Hi ,Joel 

    Yes the SDO data is wrong when I set the boud rate to be 8M , from the SDO waveform the bits are all high and I read  AIN0-AIN2 to be the same .( 19995)

    see below host app reading  CH0~CH2  : 

    Actually the CH0  and CH1 are DC signal range from -0.5V to 0Vdc   with  1 V DC bias;CH2 are DC signal range from 0 to 0.9V dc.

    what I am  reading is only inital condition with no signal input , that is  CH0& CH1 should be around 1V and CH2 should be around 0V .

    below reading is normal 

    the problem is some of the IC  cannot support 8M SPI boud rate, when decrease to 4M , the reading value recovery to normal . 

    THE TLV2548 Configuration Register bit definitions as below:

    D11 : 1 internal ;D10 : 1 internal ref =2V ;D9 :0; D8,7 :  00  internal OSC;D6,5 :00  Single short mode; D4,3 : 00  Sweep auto sequence select 0-12-3-4-5-6-7;

    D2: 0 ; D1,0 : 00, 

  • Hi Hong,

    Thanks for the information. This device uses SPI Mode 0 (CPOL = 0, CPHA = 0). Currently, it looks like you are providing SDI at the falling edges of SCLK. At slower clock speeds, it might still be read, but at higher speeds it might not. Could you try providing SDI on the rising edges of SCLK instead? 

    Regards,
    Joel

  • Hi, Joel,

    Do you mean try to set up SPI to be SPI Mode 01 (CPOL = 0, CPHA = 1)? I have tried all the four mode (CPOL=0, CPHA=0; CPOL=0, CPHA=1; CPOL=1, CPHA=0; CPOL=01,CPHA=1, but it looks TLV2548 only support CPOL=0.

    I have set mode CPOL=0, CPHA=1 it looks the same as before(CPOL=0, CPHA=0). that is, at 4M baud rate, SDO reading correct, at 8M baud rate, SDO reading all high,see below OSC snapshoot .

    4M baud rate  (CPOL=0, CPHA=1):  SDI on the rising edge of SCLK

    8M baud rate (CPOL=0, CPHA=1), SDO not correct (all bits high)

    Regards,

    Hong

  • Hi Hong.

    What is the status of FS during these conversions? When FS is not in use, it should be tied to Vcc per the datasheet. In the case that FS is held high, the device follows SPI Mode 0, where SCLK idles low and data is clocked on rising edges. If you are using FS otherwise, please let me know. 

    Regards,
    Joel

  • Hi, Joel ,

    FS, CSTART and PWDN(Pin 17, 14 ,16) are all connected to +5V.

    Regards

    Hong

  • Hi Hong,

    I lost track of this conversation, so apologies for not getting back to you on this. Was your issue able to be resolved? If no, I can provide further support.

    Regards,
    Joel

  • Hi, Joel ,

    thanks for getting back, But I still cannot get a fast SPI   baud rate with 8M, I use 4M only.

    Regards

    Hong

  • Hi Hong,

    Unfortunately I wasn't able to find anything else that would be wrong from your captures. My only recommendation then would be to verify your timing parameters.

    Regards,
    Joel