ADC12QJ1600EVM: ADC12QJ1600EVM

Giora Eytan

Expert 1275 points

Part Number: ADC12QJ1600EVM
Other Parts Discussed in Thread: LMK04828, ADC12QJ1600

Tool/software:

Hello,

Please explain the difference between:

1. ADC12QJxx00EVM - running with LMK for clock sourcing and GUI version 1.9.1.

2. ADC12QJxx00EVM (lidar reference) - running with built in 50Mhz clock sourcing and GUI version 1.1/1.2.

- With EVAL board number 2 choosing sampling frequency of 1Ghz and JMODE8 we are getting FPGA reference clock of 193.359375Mhz. ( 12.375GB / 64). The only options is 16,32,64)

- With EVAL board number 1 choosing sampling frequency of 1Ghz and JMODE8 we are getting FPGA reference clock of 187.5Mhz. ( 12.375GB / 66).

Why the difference between the two boards?

attached images of the boards GUI.

Regards,

Giora

over 1 year ago

+1 Eric Kleckner over 1 year ago

TI__Expert 6180 points

Hello Giora,

For the lidar reference design the only available FPGA clock source is from the trig out pins of the adc which only have the available dividers of 32, 64 and 128. For the ADC12QJ1600 EVM there is an LMK04828 option to feed the FPGA clocks so there are many more divider options available.

Best,

Eric

0 Giora Eytan over 1 year ago in reply to Eric Kleckner

Expert 1275 points

Dear Eric,

Please find here under a block diagram of the clock distribution we are intend to use in our board.

Please comment on the added jitter from the cascading the clock distribution ZL40215.

(Instead of using the LMK).

ClockScheme-V2.pdf

Regards,

Giora

+1 Eric Kleckner over 1 year ago in reply to Giora Eytan

TI__Expert 6180 points

Hello Giora,

I cannot comment on the part you mention. See the following links for analyzing jitter

https://www.tij.co.jp/jp/lit/an/slyt379/slyt379.pdf?ts=1722869476282&ref_url=https%253A%252F%252Fwww.google.com%252F

https://www.tij.co.jp/lit/an/slyt389/slyt389.pdf?ts=1722869449895&ref_url=https%253A%252F%252Fwww.google.com%252F

https://www.ti.com/lit/an/slyt422/slyt422.pdf?ts=1722869509203&ref_url=https%253A%252F%252Fwww.google.com%252F

https://www.ti.com/lit/an/slyt705/slyt705.pdf?ts=1722869368036&ref_url=https%253A%252F%252Fwww.google.com%252F

About you block diagram SYSREF is an input to the FPGA, not an output from the FPGA. Typically we would use a clocking chip to route all of the ADC sysref and FPGA SYSREF from a common source.

Best,

Eric

0 Rob Reeder over 1 year ago in reply to Eric Kleckner

TI__Mastermind 41280 points

Hi Giora,

I believe the papers that Eric suggested spells out how to do a jitter analysis on your clock distribution design.

Simply RSS (root-sum-square) each clocking device as they cascade to each other, the sum total jitter will be the jitter presented to the ADC.

This total jitter will then have the impact on the sampled signal. In general as the analog input signal goes higher in frequency, the SNR will degrade.

Here are a few more papers that help understand the degradation.

https://www.analog.com/media/en/technical-documentation/application-notes/AN-501.pdf

https://www.analog.com/media/en/technical-documentation/application-notes/AN-756.pdf

www.analog.com/.../analog-to-digital-converter-clock-optimization.pdf

Regards,

Rob

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ADC12QJ1600EVM: ADC12QJ1600EVM