Part Number: ADC128S102QML-SP
Tool/software:
Hi, in a few words I would like to use the ADC in a lower resolution mode.
From the datasheet I understand that a frame is delimited by CS but also that it must be 16 clock cycles long:
"A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain an integer multiple of 16 rising SCLK edges."
But from the following sentence it also seems that for the control register only 8 clock cycles are sufficient:
"During each conversion, data is clocked into a control register through the DIN pin on the first 8 rising edges of SCLK after the fall of CS."
Can I end a conversion early with CS if I don't need the full ADC resolution?
In other words, can I use the ADC like in the following timing diagram? Here I'm only using 8 clock cycles thus 4 output bits as an example. SDI and SCLK have an high idle state.
And for example if my SCLK frequency is 800kHz and I use 4 channels at 8 bits of resolution (12 SCLK cycles + 1 CS cycle) does that mean that my conversion frequency is 61.538kHz and my sampling frequency is 15.384kHz per channel?
Best regards
