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ADS1298: Getting noise while collecting data from ads1298.

Part Number: ADS1298

Tool/software:

Hi,

I am using ADS1298ECG-FE Board And applying +/-500mV sine wave at 100Hz frequency at input as shown below in figure-1.


Figure-1 : Input of ADS1298

We are able to achieve complete sine wave in EVK as applied to input. Output of EVK kit is shown in figure-2.


Figure-2 : Output of EVK Kit from Software

But when we use ADS1298 Board with the Nordic NRF52840-DK Noise is Affecting our signal. We are collecting data through SPI and sending data to USB through NRF, After that we are plotting the graph and the noise is visible in the graph as shown in figure-3 provided below.

Figure-3 : Output Of USB captured through NRF

I Found that there is on Board DSP in EVK kit, So is there any kind of mechanism provided in DSP software to filter out noise?  If yes, what is it?

We have done complete jumper setting as mentioned in datasheet as well as Ti Fourm. Below is the register configurations we have done.

conf|config1	0x01	0x81
conf|config2	0x02	0x10
conf|config3	0x03	0xDC
conf|loff	0x04	0x03
conf|ch1set	0x05	0x20
conf|ch2set	0x06	0xA0
conf|ch3set	0x07	0xA0
conf|ch4set	0x08	0xA0
conf|ch5set	0x09	0xA0
conf|ch6set	0x0A	0xA0
conf|ch7set	0x0B	0xA0
conf|ch8set	0x0C	0xA0
conf|rldsensp	0x0D	0xFF
conf|rldsensn	0x0E	0xFF
conf|loffsensp	0x0F	0xFF
conf|loffsensn	0x10	0x02
conf|loffflip	0x11	0x00
conf|gpio	0x14	0x00
conf|pace	0x15	0x00
conf|resp	0x16	0xF0
conf|config4	0x17	0x22
conf|wct1	0x18	0x0A
conf|wct2	0x19	0xE3
  • Hello Ajay,

    This appears to be an SPI capture issue and not a noise issue. You have validated that such noise transients are not present in the analog domain as seen on the oscilloscope capture. Furthermore, the same settings were validated on the ADS1298 evaluation platform. 

    I've zoomed in below to highlight a couple instances where the output data suddenly jumps. This can happen when a new conversion completes while the previous conversion is being read. Check the timing between nDRDY and completion of the 216-bit data frame to ensure that you are not coming close to overlapping the next conversion. The output shift register is immediately updated when the nDRDY falling edge occurs.

    Regards,

    Ryan