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ADS7038: Can host device append CRC when CRC is disabled on ADS7038?

Nestor Chacin
Prodigy 10 points
Part Number: ADS7038


Tool/software:

I am trying to minimize the number of cases my device needs to handle. For example, I would like to send the same message to trigger a reset in the ADS7038 whether CRC is enabled or disabled. Is this possible? In other words, when CRC is disabled, would appended CRC bits from the host device be treated as "don't cares"?

  • 0
    TI__Genius 16910 points

    Hi Nestor,

    Apologies for the delayed response. When you say you want to reset the device, are you referring to setting the RST bit in the GENERAL_CFG register? If so, what is the bit stream you plan to send to set this bit, and are you using the set bit command or the register write command for this?

    Regards,
    Joel

  • 0
    Prodigy 10 points

    Hi Joel,

    I'm attempting to reset the device by setting the RST bit in the GENERAL_CFG register. The situation: The master (host) device does not know whether the ADS7038 is in CRC mode (This could happen if the master device may has been reset). If I send the message with CRC 0x180101E1 (set bit opcode, GENERAL_CFG address, mask, CRC), will the ADS7038 interpret the bitstream correctly regardless of its current CRC mode? that is, if it is in CRC mode, the CRC check is successful and the reset is triggered - and if it is not in CRC mode, the CRC bits I appended are ignored and a reset is triggered from the message in the first 24 bits?

    Thanks! 

  • +1 in reply to Nestor Chacin
    TI__Genius 16910 points

    Hi Nestor,

    Understood. Overall, there are 4 CRC status combinations that determine whether a SPI command is parsed correctly.

    1. Host CRC off & device CRC off: this would just be a normal instruction

    2. Host CRC off & device CRC on: this would yield a CRC error, and handling it i described in the "CRC on Data Interface" section of the datasheet

    3. Host CRC on & device CRC off: this is the situation which we would like to investigate

    4. Host CRC on & device CRC on: provided the correct 8-bit CRC, communications function correctly

    To test case number 3, I used register 0 as a test register, as it returns 0x81 by default, which I verified. While ADS7038 CRC was off, I sent a 32-bit data stream 0x08000156. The first three bytes are a write instruction to turn off the BOR bit in the SYSTEM_STATUS register (0x00). The fourth byte is the corresponding 8-bit CRC value for the previous 24 bits. If the last byte was a don't care, I would see the SYSTEM_STATUS register return 0x80 on the next read. 

    After another SYSTEM_STATUS register read, the register returned 0x81 again. I tried again to clear the last bit with a 24-bit write instruction this time (without the CRC byte) and upon another reg read, the register now returned 0x80.

    Since the RST bit in the GENERAL_CFG bit is changed as with any other register, I would expect that if you appended an 8-bit CRC to a 24-bit instruction (32-bit frame) while the device is not in CRC mode, it would not recognize this instruction and do nothing. Therefore, I suggest you add some conditional logic to this operation on the controller's side to determine whether the device is in CRC mode.

    Regards,
    Joel