Other Parts Discussed in Thread: DAC8568
Tool/software:
Hi all,
I am currently working on a product design integrating the ADS8332 8-ch ADC and the DAC8568 8-ch buffered DAC, but hitting road bumps with the former's various timing requirements in particular, which I guess to some extent is due to it being an older design.
My needs are fairly simple - a bit simplified, I basically have a free-running combined DAC/ADC processing loop where the DAC is updated at the start of the cycle and the ADC read at the end of the cycle, as this design allows for the lowest possible inter-cycle latency in e.g. analog control scenarios, while additional digital processing can happen in between these two in preparation for the next updating cycle. For this exercise, you can also assume that this combined processing loop runs at rates sufficient for good quality audio, even if it also covers non-audio duties. You should also be aware that due to many other SPI devices being used in the overall product, it employs a multiplexed /CS design i.e. the SPI HW does not directly control the individual /CS for each device; instead this happens via MCU GPIO's multiplexed via 74138's or similar. Anyway, my questions then are as follows:
(1) All eight DAC channels need to be jointly updated every cycle, which means that the DAC8568 requirement of having a /CS flip for every individual channel update, while workable, is less than ideal - it would be much preferable to push the data for all channels at once to reduce the overall processing time required, but I'm not sure if there's an equivalent buffered SPI DAC in the TI portfolio that can do that?
(2) As for the ADC, I would ideally like to have the same, i.e. being able to fetch the latest state of all eight channels in one go, for every cycle, having e.g. triggered a new sampling round as a last step of the prior cycle, in preparation for the next. If this is not feasible, I could perhaps live with only two of the ADC channels being fetched every cycle, while the other six ADC channels could e.g. be fetched in a round robin fashion, one per cycle. As my SW design is free-running and hence do not use HW interrupts, I would also like to avoid any hardware pin related requirements / dependencies like the ones on the ADS8332, cf. e.g. its implicit timing requirements vs /CONVST/EOC/etc, which again I don't have a need for in this design and hence only adds design complexity. This is where I'm personally hitting slightly thin ice though, given the sheer size of the TI portfolio and the various implications of part selection including lifecycle considerations etc. For example, would e.g. something like the ADS706x suffice here, or are there better alternatives given the needs outlined above? (i.e. all in all updating 8 SPI DAC channels and 8 SPI ADC channels in the fastest and simplest way as part of a free-running SW design).
(3) Of course, if there are instead / also some smart(er) SW related aspects to the above that I may have missed, please feel free to enlighten me! 
Thanks in advance!
BR//Karl
