DAC80004EVM: controlling DAC8004 EVM using esp8266 nodemcu

Hello ,I want to make command 4 shown below,my goal is purely see voltage out put on channel 0.
How LDAC and CLR needs to be connected?

Hi Yefim, 

CLR is a falling edge signal to clear the DAC to 0V. Keep this pin high on the EVM. 

LDAC is an active low pin to load the DAC value with the value from the input shift register. Keep this pin always low if you want the input register and DAC output register to be transparent.

Best,

Katlynne Jones

Hello,regarding the SYNC(CS) pin .Its shown in the white wire as shown in the photo.
no jumper connecting two pins of JP4.

Also JP5 pin2 connecting directly to GND as shown below in blue wire.

Is it ok?
Thanks.

Hi Yefim, 

Your CS (SYNC) connection is good.

JP6 is a jumper that will connect LDAC to GND when closed. It looks like it is closed in you picture, so you do not need the blue wire.

CLR is connected with a pullup resistor to VDD, so it will be high by default as long as JP7 is open. 

Best,

Katlynne Jones

Hello , i want to send a shown below command 4th in the table below  ,very important clock and data relations.
Is it ok?
00000011 00001111 11111111 11110000

FULL transmition:

PARTIAL

Hi Yefim, 

The data format looks ok to me. The data is updating on the rising edge and the DAC will capture the data on the rising edge. I see the 00000011 00001111 11111111 11110000 command. 

I can't see the time scale, or the SYNC signal. So just make sure you are meeting these timing requirements: 

Are you supplying the VDD pin of the EVM with an external supply? 

Best,

Katlynne Jones

Yes, I am supplying from ESP8266 board. have connected all the rest as shown below and i measue from J1A pin 8 (outputA) and i get 1.65 constant

Althought i send 

buf[3] = 0b11110000 # B7_B0
buf[2] = 0b0000111 # B15_B8
buf[1] = 0b00000000 # B23_B16
buf[0] = 0b00000011 # B31_B24

Where can it go wrong?

Thanks.

chip select :

3.3v connection:


GND connection from esp8266 board:





CLR: J2A pin 19 3.3V


LDAC is connected to gnd

Hi Yefim, 

You have the reference pin connected to the 5V reference via JP2. With your 3.3V VDD supply, I suspect that the reference is actually clipping to 3.3V. The POR is connected to VDD (via JP3), which means the device will reset to midscale. 1.65V makes sense for a 3.3V reference. I would assume that the SPI communication is not working. 

Can you remove the wires connected to CLR and LDAC to reduce the total amount of wires in the picture. CLR and LDAC are already connected to the correct voltage on the board itself with these resistors/jumpers:

After that, can you send a picture and label each wire? 

It looks like you might have the J2A header connections wrong. Make sure you pay attention to where the pin 1 marking is on the header. It is hard for me to see in your screenshots though, and not all of the wires are labeled. The SCLK and MOSI/MISO should be connected as shown here:

Best,

Katlynne Jones