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ADS131M08: We would like to have a detailed understanding of the synchronous sampling mechanism inside the ADC.

user4637774
Intellectual 360 points
Part Number: ADS131M08

Tool/software:

Our board uses four ADS131M08, and our product requires four ADCs to achieve accurate synchronization. The four ADCs use the same clock: 8.192M. The sample rate is 8KSPS. The 4-way ADC is synchronized after the boot initialization, that is, a low pulse is given to the sync pin. As a result, it can be seen that the drdy foot of the 4-way ADC is triggered synchronously. Next, we would like to have a detailed understanding of the synchronous sampling mechanism inside the ADC.

1. Since ADS131 is a sigmaDelta ADC, oversampling technology is used for internal sampling. Is the first sampling point between these ADCs or between channels synchronized?

2. What is the oversampling time span of a transformation? 3.Do the sampling intervals between channels shift more and more over time?

  • 0
    TI__Mastermind 41831 points

    Hi user4637774,

    Answers to your questions (most of which can be found in section 8.5.2 in the ADS131M08 datasheet):

    user4637774 said:
    Since ADS131 is a sigmaDelta ADC, oversampling technology is used for internal sampling. Is the first sampling point between these ADCs or between channels synchronized?

    I'm not sure I understand what you are asking here. The ADS131M08 has 8x ADCs in the same package, so the "ADCs" are the same as the "channels". The synchronization event actually synchronizes the start of conversion, or when the ADCs begin the conversion process

    user4637774 said:
    What is the oversampling time span of a transformation

    The ADS131M08 uses a sinc3 filter, and therefore takes 3 conversions to settle after a sync event

    user4637774 said:
    Do the sampling intervals between channels shift more and more over time

    The timing (number of modulator clocks) should be the same for all devices. You are using the same clock for all 4x ADCs, which ensures the highest level of synchronization between them. However, it might be possible for the ADCs to be asynchronous if the trace length for each clock is very different. For example, if 3x ADCs are very close to the clock source, but one ADC is very far away, it is possible that the last ADC might get out of synchronization with the first ADC.

    However, this is probably very unlikely, but it might be useful to pulse the SYNC pin on occasion to ensure the ADCs are in sync. If the SYNC pulse edge coincides with the ADC internal clock edge, nothing will happen because the device is already in sync.

    -Bryan