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DAC39RF10EVM: How to control LMX1204 in DAC39RF10EVM

Part Number: DAC39RF10EVM
Other Parts Discussed in Thread: LMX1204

Tool/software:

Dear Specialists,

I am evaluating with DAC39RF10EVM.

I want to control a PLL called LMX1204 in DAC39RF10EVM.

I want to change to multiply mode on the LMX1204 to quadruple the input clock and output to the DAC.

I tried to write in the GUI of the DAC39RF10EVM according to the procedure written in the LMX1204 catalog, but I could not get it to multiply mode.

The specific order is,
(1) The values of R33, R34 and R67 were changed.
(2) The values of R2 and R3 dividers were made to fit within the state machine clock constraints.
(3) Reset was performed on R0.
(4) The CLK_MUX of R25 was changed to the multiplier mode.

Can someone please tell me what's going on?

I appreciate your great help in advance.

Best regards,

masa

  • Hello Masa, 

    The LMX1204 on the DAC39RF10EVM uses a PLL to do frequency multiplication as you described. The VCO range of that PLL is 3.2 GHz to 6.4GHz. So it can only multiply when the output frequency is within that range. If it is outside of that range the VCO will not lock. The LMX1204 is typically just used for its clock/sysref distribution as well as the logic clock generation circuit as it can support up to 12.8GHz in distribution mode. 

    If you plan to use the multiplier within the range of the multiplier VCO could you tell me your input frequency? I can try to duplicate the setup. 
    Regards, 

    Matt

  • Matt,

    Thanks for your valuable reply.

    The input frequency of 1.8 GHz is multiplied by 2 to output 3.6 GHz.

    After performing a reset on R0, any register reads in the GUI will be 0x00.
    So I'm assuming I'm doing something wrong while performing the reset.

    Regards,

    masa

  • Hey Masa, 

    After reset the MUXOUT_EN field (bit 13 of register R23) on the LMX1204 is 0. This bit will need to be programmed right after reset to enable readback. 

    In addition the MUXOUT_SEL field (bit 6 of the same register) also needs to be set. 

    Programming 0x6040 to register R23 should fix both issues and enable readback. 

    To get the multiplier to work. First set, and unset the field CLK_DIV_RST. (Field 6 of R25)

    Then program 0x51CB to register R67

    0x0005 to register R34

    0x5666 to R33

    Then program the field CLK_MUX to 0x3 (bits 5:3 of R25)

    One this is done set the SMCLK_DIV and SMCLK_EN fields accordingly based off the datasheet. (found in R2 and R3)

    Finally write 0x00 to 0x00 to force VCO calibration of the multiplier. 


    Once this is done, one can turn the state machine clock off (SMCLK_EN = 0) to prevent an unwanted spurs in the clock output. 

    Regards, 

    Matt