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ADS8471: CONVST jitter spec: why is it 10 ps max?

Adam Steele
Prodigy 90 points
Part Number: ADS8471

Tool/software:

This is a 1 Msps ADC. The datasheet say the 'edge jitter' must be 10 ps max.

1) I am not sure what 'edge' jitter means.  Is this a cycle-to-cycle jitter?  I'm assuming it means something like this below.

2) Why is this to tight? 10 ps is 10 ppm of 1 MHz. It seems like you can trigger CONVST at any rate you like up to a max of 1 Msps, so why would this jitter matter?   I don't even see how it could be SNR related; I am not sure i did the calculation correctly, but I believe maintaining a >93 dB SNR at 100 kHz would still only imply something like 100 ps jitter.

I wanted to use something simple like a silicon oscillator for CONVST, but the jitter of these is much higher. What are the practical performance effects if I use a clock with e.g 100 ps jitter.

I have some additional questions about the digital outputs but since that is a different topic I'll put them in  anew question.

  • 0
    TI__Expert 5860 points

    Hi Adam,

    Thanks for your question. The only thing I can think of is that a greater jitter may impact the ADCs ability to coherently sample, which may in turn affect the performance. Unfortunately, as this is an older device, the information I have is limited.

    Best regards,
    Samiha

  • 0 in reply to Samiha Sharif
    Prodigy 90 points

    Hi Samiha.  Thanks for replying.

    In that case, do you have any example boards/builds which use this part which include their BoM so I can see what clock source they use?

  • +1 in reply to Adam Steele
    TI__Expert 5860 points

    Hi Adam,

    We don't have an EVM for this ADC so I can't share a reference BOM. However, we do have an SNR vs Jitter excel calculator tool that can be used to show the SNR degradation when using a clock source with 100ps jitter, with a 100kHz input signal - the SNR will degrade from the desired 93dB to 84dB:

    The jitter specification is a 1-sigma RMS jitter, not peak to peak. Many crystal based oscillators can meet this requirement. Note: for our precision ADC portfolio, the aperture jitter may be ignored. This parameter really only matters for our higher speed ADC portfolio.

    The excel calculator I used is linked here:

     PADC Jitter and SNR calculator.xls.

    I hope this helps!

    Best regards,

    Samiha

  • 0 in reply to Samiha Sharif
    Prodigy 90 points

    Yes, this is helpful. Thank you.