Hi,
I am trying to implement the necessary code in order to connect ADS5400 and Virtex 6. I tried with the schemes posted by Richard and Simon, i.e.:
-13 IBUFDS blocks (12 data + 1 clock)
-13 IDElAY blocks
-1 BUFIO block
-1 BUFR block
-12 IDDR blocks
When I try to implemt the design I have this error map:
LIT:534 - BUFIODQS symbol "BUFIO_inst_clock" (output signal=clock_bufio)
cannot drive a BUFR. Please modify your design to avoid this unroutable
situation.
Can I connect directly BUFIO and BUFR? This is a difference between both of schemes, Richard doesn't use BUFR and Simon does. I'm not sure if I must use this block. If I delete BUFR I have the next two errors:
Place:1362 - IO Clock Net "clock_bufio" drives a load pin on a component
("clock_bufio_out_OBUF" type-LUT) that is not on any IO column.
To debug your design with partially routed design, please try to allow
map/placer to finish the execution (by setting environment variable
XIL_PAR_DEBUG_IOCLKPLACER to 1).
Pack:1654 - The timing-driven placement phase encountered an error.
If you think it is neccesary, I will post the code, but I can comment the more particular things now:
-About IBUFS, I obtain the same result using generic map or not :
--generic (IOSTANDARD : string := "LVDS_25"; IFD_DELAY_VALUE: string := "0"; DIFF_TERM: boolean := FALSE)
-Is this ok?
-About IDELAY, at the beginning I am using DEFAULT mode. I think I will need the FIXED or VARIABLE modes, but I don't know exactly how I can instantiate the IDELAYCTRL. Could you tell me how can I do?
-About IDDR I am using this generic map: DDR_CLK_EDGE => "OPPOSITE EDGE", INIT_Q1 => '0', INIT_Q2 => '0', SRTYPE => "SYNC".
Thanks a lot for your help,
Jose
