The DAC3482 datasheet on page 9 says that the frequency of the Output Strobe (OSTR) cannot be any higher than fDACCLK/(8 x interp)--without any consideration of the incoming data interface bus width.
However, on page 44, the datasheet says that the frequency of OSTR cannot be any higher than fDACCLK/(16 x interp) when the incoming data bus is in World(sic)-Wide Mode. There look to be several errors on this page, but we need confirmation from you as to this requirement. Could you provide this please?
With the 16x factor and a 4x interpolation, we would need to create a clock that's at least 64 times slower than DACCLK--which we can't do with our currently selected clock generator. If we're supposed to instead use the 8x factor from page 9, then we're good.
Thanks and Best Regards, Tim Starr on behalf of JG@BD
