Tool/software:
Hello!
I have been using the ADS52J90 on a custom PCBA, and we have so far tested the design on about 15 or so PCBAs. I recently found that, on one PCBA, the clock to data delay varies after power on and initialization of the ADC. We have narrowed down the issue to a single ADC and have only seen this behavior on this one ADC across all of the PCBAs tested so far. Our FPGA receiver module provides the sampling clock to this ADC and performs an initialization sequence to start de-serializing the ADC data into separate channels (we are using 32 input mode), and by using the ADC's internal test pattern modes we are able to "lock" onto the bits corresponding to individual samples and then run indefinitely. Since the FPGA provides the sampling clock to the ADC directly, the ADC data clock and the FPGA deserializer do not slowly get out of sync over time. We have not previously noticed any issues with this startup alignment routine, even after running while continuously checking the received ramp pattern for bit hours for a day straight.
However, the problem that we are noticing now appears only a few minutes after the alignment routine successfully locks onto the incoming samples, which tells us that the ADC does not have a constant delay between its DCLK edges and the DATA lane edges, causing our deserializer state machine to start receiving skewed data. We have probed the power rails for the ADC, checked the temperature of the unit during this behavior, and have narrowed down the behavior to this specific ADC exhibiting a varying DCLK to DATA timing relationship.
Given that the ADS52J90 datasheet calls out tPROP and delta_tPROP as typical values, is there any measurement data on how tPROP varies over time or temperature for a single ADC? Since we have not seen this behavior before on any of our ADCs, are we to assume that this ADC has been damaged in some way?
Best,
Austen
