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DAC39RF10: DDS mode questions about current consumption

Part Number: DAC39RF10
Other Parts Discussed in Thread: DAC39RFS10, DAC39RF12, DAC39RFS12

Tool/software:

Hi,

the following questions refer to devices DAC39RF10 / DAC39RFS10 as well as DAC39RF12 / DAC39RFS12:

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It is mentioned in the data sheet that the chips can also operate in pure DDS mode. Datasheet section 7.4.1 briefly lists a few differences from DUC mode.

  1. I would be interested in what the current consumption of the chip looks like in DDS mode.
    For example, in case that the output CW signal is about 10 GHz and you select the CLK so that the signal is in the 2nd Nyquist zone.
  2. How does the current consumption generally scale between DUC and DDS mode for the individual circuit parts (NCO, DUC, with and without JESD interface, etc.)?
  3. The data sheet also lists chips called "DDS", which are probably only intended for DDS operation.
    Do you have any further information? Are the same chips only "selected" (e.g. defective DUC path) or own designs? Is there a separate data sheet for this?

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Best regards

  • Hey franziskus, 

    DDS mode does use quite a bit less power then when the JESD subsystem is running. Increasing the number of active DUCs will cause the device to use more power, but its not a significant amount. I have a board here that has a 12V input and I see the total system current go up a few mA as I active each DUC (change JESD_M from 2 to 4 to 6 and to 8).

    Typical chip power will be around 2W maybe up to 2.2W in DDS mode. 

    VDDDIG will pull around 1.3A @ 1V so that's most the power. 

    VDDCLK10 will pull around 350mA @ 1V

    VDDLA and VDDLB will pull around 200mA

    The 1.8V supplies will all pull around 100mA (typically just under)

    There are DDS spins of the DAC that have not released yet but should shortly. 

    Regards, 

    Matt

  • Thanks Matt, this helps!

    Best regards