ADC3444EVM: Incorrect data capture using ADC3444

uts driver

Part Number: ADC3444EVM
Other Parts Discussed in Thread: ADC3444

Tool/software:

Hello ,

Iam using ADC3444 with zynq 7000 series FPGA using FMC ADC adapter. I have studied how to deserialize high speed ADC related articles and implemented in xilinx vivado platform. I tried to test the design using test patterns available in ADC3000 gui. Iam able to get all 0's, all 1's and toggle pattern correct output but unable to capture custom patterns. I have tried in different ways but same thing is repeated. Iam attaching the reference design code below .can I use ADC3444 evm directly or any hardware changes like attaching resistors or capacitors.Does the EVM directly works or it requires any registers to set initially before using it. If you find anything missing in below reference design please let me know.

reference design : https://github.com/cjhonlyone/ADC-lvds

over 1 year ago

0 Chase W over 1 year ago

TI__Mastermind 24010 points

Hi,

If you can achieve the test pattern outputs correctly on all lanes then your hardware is ok. For help with fpga you’ll have to go to AMD/Xilinx for assistance.

Thanks, Chase

0 uts driver over 1 year ago in reply to Chase W

Prodigy 80 points

hello chase,

thanks for your reply. The problem is not with FPGA . we are able to get the data but the bits are shifted. we are deserializing the data taking frame clock as reference. I think frame clock and data are not aligned due to which bits are getting shifted. I found a related forum in which bits are getting shifted is the issue. In that forum it was advised to reset the serdes blocks. I have tried that but each reset gives me a different alignment.. Also we can't check every time whether data is aligned or not . so is there any robust solution. Iam attaching the similar issue forum link below.

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/871698/adc3424-misalignment-of-data-channels-and-frame-clock

thank you

0 uts driver over 1 year ago in reply to uts driver

Prodigy 80 points

Hii

A small change alignment is not changing even though reset is applied . Data is shifted arithmetically left by 2 bits and it remains same after reset also. This is observed in all the 4 channels.

thank you

0 Rob Reeder over 1 year ago in reply to uts driver

TI__Mastermind 41940 points

Hi,

I am not sure the Chase's question was answered. If you put the ADC in test pattern mode, for instance, ramp mode test pattern. Is the data capture and ramp display correct? Can you send us a plot to validate this point?

Thanks,

Rob

0 uts driver over 1 year ago in reply to Rob Reeder

Prodigy 80 points

Hello ,

Sorry for the late reply. Actually what I am saying is that there is some delay between adc frame clock and adc data and the delay is constant , it is of one dclk period.when we adjusted this delay in data path we are able to get correct data. All the test patterns are validated and even external signal is also captured perfectly. As it is mentioned in data sheet that data and frame clock are aligned I just want to clear with you regarding this delay whether this delay is common or not.

Best regards.

0 Rob Reeder over 1 year ago in reply to uts driver

TI__Mastermind 41940 points

Hi,

I am checking on this for you through design.

Please give me a few days to respond back.

Regards,

Rob

0 Rob Reeder over 1 year ago in reply to Rob Reeder

TI__Mastermind 41940 points

Hi,

Please check the polarity, P/N connections, of both the DCLK & FCLK from the ADC and make sure it is connected correctly. This could be the source of the delay.

Regards,

Rob

0 uts driver over 1 year ago in reply to Rob Reeder

Prodigy 80 points

Hello ,

The polarity connections both P and N are correctly routed. The delay of one dclk is observed in the case when I try to use ADC with a sampling rate of 100msps. when I use adc with 125msps i didnot observe any delay. Both fclk and data are aligned in the case of 125msps but one clock delay is observed in the case of 100msps. I can adjust this delay using idelaye2.But want to know why this is happening at 100msps rate and not at 125msps.

Best regards.

0 Rob Reeder over 1 year ago in reply to uts driver

TI__Mastermind 41940 points

Hi,

Thank you for checking the polarity. Let me look into why this might be happening at the reduced sampling rate.

Please give me a few days to respond back.

Regards,

Rob

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ADC3444EVM: Incorrect data capture using ADC3444