Tool/software:
Recently, our company applied DAC3152 to design a laser, after measuring the DAC CLK, the LVDS data from the FPGA, but the DAC did not output.
The data output of the FPGA is oserdes 8:1, a combination of 4 bits on the rising edge + 4 bits on the falling edge, oserdes serclk 300M, and 1/4 serclk on the aligned clock.
Can you help analyze what the problem is and find the cause from there.
I have done the RF_driver.pdffollowing test, AVDD 3.3V is 3.25V, DVDD1.8V is actually 1.76V, sleep pulls up 100K.