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problem in interfacing the DAC3484 with xilinx ML605

SRIDHAR KUPPALA
Prodigy 65 points

Other Parts Discussed in Thread: DAC3484, CDCE62005, DAC3283, DAC3282

Dear sir,

i need to implement the sine function for generation for sine waves at a frequency of 50 MHz.

the sine wave function is implemented in FPGA ( XILNX ML605 ) and the digital data is given to the dac3484.

it is observed that the output of dac not a sine wave but some noise is generated.

from dac3484evm the 307.2 MHz is given to FPGA through cdce62005 and signal processing is done at 307.2 MHz.

the data is output to the dac at 614.4 MHz in DDR mode. the dac is given an update rate clock of 1.2288 GHz.

the way iam working is correct or not.

iam thinking that there is some interfacing problem.

do you have any reference design for ML605 with DAC3485.

please help to solve the problem

 

 

with regards

k sridhar

  • 0
    Prodigy 65 points

     

     

    And also please suggest the possible XILINX  EVMS that can be interfaced with dac3484

  • 0 in reply to SRIDHAR KUPPALA
    TI__Genius 12965 points

    Sridhar,

     

    We have worked with Avnet on Speedway which demos how to connect our high speed data converters to the ML605 kit (google avnet speedway)  The demo involves working with the DAC3283 and ADS62P69.  If you already have the ML605, you will need the adapter boards and ADC/DAC EVMs in the kit TSW4200 which can be found on ti.com.

     

    I can get you in touch with a local Avnet Xilinx specialist who can provide some assistance with your project.  Where are you located?  I can pass your info to the approriate local Avnet Field apps engineer who can provide better support on your Xilinx needs.

     

    Once you are familiar with the DACA3283 the DAC3484 is just a data formatting issue.

     

    Regards,

    Ken.

  • 0 in reply to Ken C
    Prodigy 65 points

    hi ken,

     

    iam located in hyderabad, india. can you please provide the demo information to us so that it will be help full to us

     

    regards

    sridhar

  • 0 in reply to SRIDHAR KUPPALA
    Prodigy 65 points

    hi ken

     

    if u r having the source code for interfacing the fpga with dac3283 please provide the information which will be helpful to our project

  • 0 in reply to SRIDHAR KUPPALA
    TI__Guru* 83855 points

    Hi Sridhar,

    The noise could be caused by the interface timing. The DAC3484 has internal DATA or DATACLK delay that can be used to adjust the correct setup and hold time. The delay register is located in register config36, and the required setup/hold time for each setting is listed on page 10 of the datasheet. 

    Typically, for edge aligned data, the DATACLK delay setting of 160ps (i.e. config36 = 0x1000) would work. Each delay step is approximately 40ps to allow fine tuning of the interface timing.

    Another way to test the functionality of the DAC is to use the constant input function with NCO. In the GUI, under Input > Input Format, you can enable constant input and type in the digital code that you need. For instance, in 2's complement, you can type in 32768. You can then enable the NCO and set the NCO frequency to be 50MHz to see if there is a 50MHz tone at the DAC output. 

    If you can save the current register of the DAC3484 setup, I can help review your settings to make sure the DAC is configured correctly. 

     

    -KH

    DAC3484 NCO.ppt
  • 0 in reply to Kang Hsia
    TI__Genius 12965 points

    Sridhar,

     

    Please contact this local India Avnet Field apps.  They should have some familiarity with the ML605 and DAC3282 in the speedway examples.

     

    Soumitra Das Soumitra.Das@avnet.com

    Bangalore, India

     

    Regards,

    Ken.