ADC12DJ5200-SP: CLK_P/N and SYSREF Input Waveforms

Hi Joseph,

I am looking into this for you. Typically we recommend a DC coupled signal for these pins which is non-standard LVDS or PECL.

You may want to use a amplifier for the interface to DC and do the level shifting.

Regards,

Rob

Hi Joseph,

For these signals we typically AC couple them from a clocking chip and let the ADC self bias these pins to the correct voltage. Can you share which specs you are specifically concerned about in the datasheet?

Thanks,

Eric

See attached for the input wave form being fed to the ADC CLK_P/n pins from the LMX2615.

Hi Joseph,

If you plan to use an LVPECL style output, then you need to pull the outputs directly to ground, thru a DC path. 

For example, 150 to 240ohm pulldown on each output leg.

The termination style you have in the pics above are for a CML based clock output.

I will hand this off to the clocking team that covers the LMX/LMK device to give you better guidance.

Thanks,

Rob

Joseph,

Both the clock and SYSREF output of the LMX2615-SP are open collector.  The pull-up component connects to 3.3 V.  There is a DC bias level but it can change with frequency and even more so with the output power setting;  it is not really intended to be used for DC coupling.

Sorry, system cut me off.  So if you have to have a pull-up to Vcc for the LMX2615-SP, then putting a DC path to ground might not go well.  That's why the AC coupling.   The output power is programmable through the OUTx_PWR setting

Rob thanks.  Also, there's a couple IBIS models for the LMX part what is the difference between the MPR and MLS versions of the model.  Also, the LMX is supposed to have an amplifier on the RF Outputs.  How do I deploy this capability in the IBIS models?

I think I fixed the ckt.  Do you agree this will work?

This actually didn't quite work on the board itself so I'll need to know how to adjust the LMX output gain in the IBIS model.