Tool/software:
Hey team,
A customer is using the ADS131m02 and running into an issue where things are going great until they receive a very low data reading.
They noted section 8.3.5 of the datasheet that state the master clock must be synchronous with SCLK. In their application they use a default crystal on the board to generate the master clock and then using a clock from the processor the generate the SPI SCLK. This results in the clocks being asynchronous.
Are they correct in this being the main issue?
The input signal to the ADC is a DC voltage that varies from 0.1V to 0.5V. They are using this to validate the firmware before stitching to AC voltage inputs. The OSR is set to 256 for 16kHz sample rates.
Thanks,
Cam