Other Parts Discussed in Thread: DAC38J84
Tool/software:
Hi there
We are working with DAC38J84EVM and we have a limitation that the SYNC signal from DAC is mapped on FMC, but on the FPGA eval board we are using doesn't have pins connected on FPGA. So we are planning to tap the CMOS_SYNC_AB and CMOS_SYNC_CD from J21 header and map it on CPLD J24 connector and then route inside the CPLD these signal to FMC_B5 and FMC_B6 pins because these pins are connected on the FPGA side.
So we have few queries regarding this scheme :-
1. Can you share the latest CPLD design files that is already flashed by TI inside CPLD, so we can do modifications inside the code.
2. Is this scheme possible, will there be any limitation in doing it this way.
3. Is there any other way out so send the SYNC signal to our FPGA
I have attached the pin mapping details of FPGA to FMC to DAC Eval board
An early response will be highly appreciated.
Thanks
