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ADS127L18: coherent sampling

Stone Zeng
Prodigy 700 points
Part Number: ADS127L18
Other Parts Discussed in Thread: CDCE6214

Tool/software:

Hi Team,

my customer is using AD7771 in power quality equipment, AD7771 has flexible SRC to achieve a coherent sampling. we promote ADS127L18 to replace AD7771 and customer think the performance is good , could you please give guidance for ADS127L18 to achieve coherent sampling? 

ps: Power line frequency range( 40HZ~72Hz), 1000 sampling points.

Stone

  • 0
    TI__Mastermind 46930 points

    Hello Stone,

    Can you let us know who the customer is in the Notes?

    The ADS127L18 does not have an internal SRC, so this function will need to be external.  Since the output data rate is proportional to the CLKIN frequency, you can adjust this clock frequency to produce an exact output data rate, based on the input sampling frequency.

    For example, using a standard clock frequency of 25.6MHz and an OSR setting of 128, the output data rate will be 100ksps.  If you wanted to adjust the output data rate to an exact value of 72*1000=72ksps, then you would adjust the input frequency to 25.6MHz*72k/100k=18.432MHz.  This frequency can be sourced by a clock generator, such as CDCE6214.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    TI__Prodigy 700 points

    Hi Keith,

    As mentioned before, the powerline frequency is 40HZ to 72Hz, and minimum resolution is 0.01HZ,  which need clock frequency range from 12.288MHZ to 18.432MHZ with 1.28k step, can CDCD6214 meet this?

    Stone

  • +1 in reply to Stone Zeng
    TI__Mastermind 46930 points

    Hi Stone,

    If using a programmable clock generator is acceptable to the customer, then I would suggest posting a new question specific to the CDCE6214.

    Based on my limited knowledge of the CDCE6214, you should be able to adjust the frequency to less than 1ppm; the clock generator tool lets you select frequencies with a resolution of 10Hz, which suggests the ADC data rate can be adjusted form 40kHz to 72kHz with 0.04Hz resolution.

    In order to meet full ADC performance when using OSR=128, the jitter should be 20ps-rms or lower, which should be easily met with any of the clock generators.

    Regards,
    Keith