DAC12DL3200: IOtest in DAC12DL3200

1. Sampling rate              : 3200 Msps

2. Sampling clock            : 3200 MHz

3. Frequency Range        : 0-750 MHz

4. LMODE                        : Dual channel,4 bus mode.

5. LWIDTH                       : 12-bit sample width

Please note,

1. We have Dual ADC/DAC sampling in-phase and quadrature components, each working at 3200 Msps.

2. Sampling clock of 3200MHz is generated by LMK04832.  

3. Each converter utilizes two buses, resulting in a total of four LVDS buses being used.

4. Dual Clock Mode is disabled in DAC.

5. Data is sent by Xilinx high speed select IO wizard(HSSIO) working at an interface speed of 1600 Mbps with DDR clock.

Register map we used for initialization and for running IO test is given below,

3. Assert Reset
0x0000B0

4. De-assert Reset – Fuse ROM load will automatically begin
0x000030

5. Program part configuration ( CH_CFG , DCM_EN , MXMODE_*, etc.)
0x010151 : configured CH_CFG
0x004800 : configured DCM_EN
0x016000 : configured MXMODE
0x017180 : configured current control for DACA
0x017280 : configured current control for DACB


6. Wait for Fuse ROM load to complete ( FUSE_DONE =1)
0x890000 : we are getting the desired output 0x03,


7. Apply LVDS signals (and SYSREF if used) to inputs. This may have been done at any earlier point if desired,
but must be stable by here.
We are giving a constant data of 0xfff to run IOtest

8. Set DP_EN =1
0x010001 : Observed LVDS_CLK_ALM as set(0xFF) here, what does that indicate?

9. Clear LVDS_CLK_ALM & STROBE_ALM
0x0821ff : Observed LVDS_CLK_ALM as high only (0xFF), why is that happening, why is it not clearing?
Our LVDS_CLK is coming from FPGA, which when observed in oscilloscope is found to be proper .

10.Synchronize the system
     a. If using LVDS Strobes for alignment:
     i. Set LVDS_STROBE_ALIGN =1
     ii. Wait for LVDS_STROBE_DET =1 
     b. If using SYSREF for alignment:
     i. See SYSREF Windowing to enable and align synchronous SYSREF capturing.
     ii. Set SYSREF_ALIGN_EN =1
     iii. Wait for SYSREF_DET =1
     iv. Set SYSREF_ALIGN_EN =0

Skipped synchronisation


11. Configure FIFO_DLY (this may be done early but should be complete by here)
0x020000

11. Configure the IOTEST data patterns in IOTEST_PAT, and IOTEST_CONT.
0x071100
0x071001

0x0720ff
0x07210f
0x0722ff
0x07230f
0x0724ff
0x07250f
0x0726ff
0x07270f
0x0728ff
0x07290f
0x072Aff
0x072B0f
0x072Cff
0x072D0f
0x072Eff
0x072F0f

12. Set IOTEST_STRB_LOCK=1 (if desired).
Not set as we are not using strobe

13. If using an LSB strobe and the pattern tests the LSb in data operation, set LSB_SYNC=0 and sync_n=1.
Skipped

14. Set IOTEST_EN=1
0x0710F1

15. Enable Transmission using txenable or TXEN_A/B.
0x022003

16. Start the test using IOTEST_TRIG.
0x071101

17. If IOTEST_CONT = 0, monitor IOTEST_RUN until the test stops and then inspect the results. If
IOTEST_CONT = 1, monitor the faults using IOTEST_SUM or IOTEST_MISS* fields in registers
IOTEST_STAT0 - IOTEST_STAT3.

IOTEST_CONT was set as 1, which is means IOTEST will run until manually stopped, yet when checked we found IOTEST_RUN 
as 0, what does that indicate,did it not run or stopped beforehand?
IOTEST_SUM and IOTEST_MISS were observed as zeros.
IOTEST_STAT0 and IOTEST_STAT3 were observed as zeros.
IOTEST_CAP registers were giving datas different from whatever was sent from FPGA.

What should i conclude from IO test and why are my clock alarms set even after clearing? why are my clock alarms set even after observing a clock in
oscilloscope?