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ADC3642: DCLK_IN generation ways

Iurii Badulin
Prodigy 20 points
Part Number: ADC3642


Tool/software:

Hi, all

Is it possible for ADC3642 in serial CMOS mode to provide DCLK_IN clock by simply connecting DCLK output to DCLK input?

Is it legal configuration, or I need to create DCLK-IN using external network form sampling clock or from FCLK?

With best regards,

Jury Badulin

  • 0
    TI__Mastermind 24120 points

    Hi Jury,

    No, this is not valid. This device does not have an internal PLL for the DCLK generation, so nothing would happen. It needs an external clock supply feeding the device.

    Thanks, Chase

  • 0 in reply to Chase W
    Prodigy 20 points

    Hi, Chase.

    Thanks for quick reply. One more question - is there any jitter requirements for DCLK_IN signal? Is it possible to generate it from sampling clock using FPGA internal PLL macros.

    Regards, Jury.

  • 0 in reply to Iurii Badulin
    TI__Intellectual 2280 points

    Hi Jury,

    There isn't a specific jitter requirement for DCLKIN. However, tPD will change based on the delay between the sample clock falling edge and the DCLKIN falling edge. Thus, the sample clock to DCLKIN relationship needs to remain consistent.

    Generating the DCLKIN from the FPGA should be okay as long as it's through a PLL that locks to the sample clock phase.

    Best regards,

    Drew