Tool/software:
Hello,
I am able to successfully read the ADC values. However, I'm not seeing the correct data rate frequency as mentioned in the datasheet. Here's some background on my setup.
I have the CLKIN frequency set to 5.102MHz. The idea behind choosing this clock was to sync the data rates to an ISR we have that's running at 39.86KHz. The formula in the datasheet for the data rate with an OSR of 64 is:
Data rate = (CLKIN / 2 * OSR) = (5.102 / 2 * 64) = 5.102 / 128 = 39.86Ksps.
However, we see the DRDY interrupts occur very haphazardly. I see the first interrupt come in at 95.31KHz and the second at 68.87KHz, and this pattern repeats. The ADC is set to 16-bit mode and 64 OSR correctly.
However, if I change the OSR to 128, and set the DRDY_FMT bit to 1 or 0, the interrupt occurs at my desired frequency correctly:
So is the data rate actually = CLKIN / OSR? Please clarify. Am I doing something wrong here?