Other Parts Discussed in Thread: AFE58JD18,
Tool/software:
Hello,
I'd like to ask what is the maximal sampling frequency at 12 bits resolution for 2-lane JESD configuration?
Best regards,
Mateusz Walczak
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In 2 lane mode 8 channel will come on each lane .So below is the calculation of lane rate;
8(No adc)* 12 (Serialization factors) * 10/8 (jesd 8 bit to 10 bit encoding) * Fs(sampling freq)
With 40MSPS we can see lane rate is 4.8GBPS. The device supports 5GBPS lane rate and that will correspond to 41.66MHz sampling frequency.
But for a shorter trace length we can push the speed till 6 GBPS. Datasheet has this information. In that case we can go till 50MHz.
40MSPS is the clock coming into the device pins, so the actual channel sampling frequency will be 20MSPS, correct ?
Is this also applicable to the AFE58JD32LP device ?
Yes correct . Each channel sampling will be half of clock frequency . Same will be applicable for AFE58JD32LP device.
Thank you. One last question, does the AFE58JD18 and AFE58JD32 share the same JESD204B block ?
We already have boards with two AFE58JD18 and would like to design a new variant that uses four AFE58JD32 or AFE58JD32LP. To do that we need to use 2 JESD lanes per device instead of 4 lanes. I would like to use our current design to test how far we can push speed of the JESD204B interface to know what will be that max possible sampling frequency when we switch to AFE58JD32.