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ADS1282-SP: Unclear parameter in Datasheet Rev.B

Hang Lin
Prodigy 20 points
Part Number: ADS1282-SP

Tool/software:

Hi,

in ADS1282-SP Datasheet Rev.B page 9, section 7.7, the parameter tDR is defined.

Below you see a reference to Table 21 for SINC filter while an equation is provided for FIR filter respectively (which I think shall be combined to get the same tDR for both filter)

My question is how tDR is calculated for each filter?

BR, Hang

  • 0
    TI__Mastermind 41090 points

    Hello Hang,

    tDR is defined in Figure 46 relative to the SYNC pin or a SYNC command.

    In the case of the SINC+FIR filter combination, you can calculate the value of tDR as provided in the datasheet:

    tDR=62.98046875/fDATA + 466/fCLK

    The SINC filter tDR values are provided in Table 21:

    tDR is based on a multiple of data rate periods, plus overhead (fCLK cycles) dependent on the details of the digital design inside the IC.  The values provided have been determined by digital design and verified by measurement. For precise values of tDR when using the SINC filter, there is not a simple equation that can be used to calculate based on the data rate.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Prodigy 20 points

    Dear Keith,

    thanks for your quick support! It would be much appreciated if you could also answer my additional 2 questions below:

    1. fCLK is dependent on the clock that user gives, fData is defined in Table 5 for Sinc, Table 6 for FIR and Table 8 for HPF.

    when using SINC+FIR filter, given fClk = 4.096Mhz, I think fDATA shall be chosen from Table 6 (saying 1000 SPS is chosen)

    then the equation would be tDR=62.98046875/fDATA + 466/fCLK = 62.98046875 * 1 ms + 466 * 244.14 ns.

    Is my calculation here correct?

    2. when using SINC filer only, tDR can be directly extracted from Table 21 (but not as a precise value)

    Given fClk = 4.096Mhz, and fData of 8000 SPS is chosen from Table 5, the tDR would roughly be 2824 * 244.14 ns.

    Is my calculation here correct?

    3. Table 5, 6 & 8 is depicited with an assumption that system clock = 4.096Mhz, accroding to 8.1.14:

    "...data conversion rate sceles directly with the CLK frequency..."

    which means if I use 2.048Mhz, the data rate is halved correspondingly, is my understanding here correct?

    Best regards,

    Hang Lin

  • +1 in reply to Hang Lin
    TI__Mastermind 41090 points

    Hello Hang,

    1.  Yes, your calculations are correct.  The data rates in Tables 5 and 6 are only valid for fCLK=4.096MHz.  If you need to calculate the data rate for different fCLK frequency in Tables 5 and 6, then fDATA=fCLK/(4*N) where N is the Decimation Ratio. 

    The HP filter is only used with the SINC+FIR, and will follow the data rates in Table 6.  Table 8 are just a few examples.  When using SINC+FIR+HP, you can set data rate to any of the values in Table 6; 250, 500, 1000, 2000, or 4000 SPS.

    2.  Yes, your calculation is correct for tDR, SINC filter, 8000 SPS.

    3.  Yes, the data rates will be 1/2 if fCLK=2.048MHz.  fDATA=fCLK/(4*N) will always give you the correct data rate for different CLK frequency and Decimation ratios (N).

    Regards,
    Keith