Tool/software:
Hi,
We are using ADC12DL2500 whose Data, Clock, Strobe signals for (A, B, C, D) Channels are connected to FPGA (XCVU23P-2FSVJ1760I) Banks. For these LVDS Signals we are not providing any 100 ohm termination between Positive/Negative (+/-) signals .In that case do we have to enable 100 ohm internal terminations present in FPGA? Kindly clarify.