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ADS52J90: ADC timing

Vlad Ardelean
Prodigy 10 points
Part Number: ADS52J90
Other Parts Discussed in Thread: THS4551, THS4509

Tool/software:

Hello,

I have a couple of quick questions regarding the ADC input stage in the ADS52J90:

1) I'm trying to simulate the ADC input stage as per the schematic in the datasheet (Figure 91, page 72). Could you please be so kind and provide me with the acquisition time and the conversion time?

The ADC will be running at 30MSPS.

2) I know the EVM recommends a THS4509RGTR for the input, but at roughly 38mA per channel, 64 channels would take a lot of power. In our application, the input signal frequency will not exceed 2.5MHz, and we are planning on running the ADC at 30MSPS, 14 bits, 64 channels. So the question is: would a THS4551 be fast enough for our application? Or, perhaps you could recommend another opamp with lower power consumption than the THS4509? Anything with an Iq lower than 10mA would be great.

Thank you very much!

Vlad Ardelean 

  • 0
    TI__Expert 7725 points

    Are you operating in 32 channel mode or 16 channel mode ?

    Do you mean System clock is 30MSPS ?

    Also can you share the details of your sensor . We can check if you directly connect the sensor to ADC as your sampling speed is comparatively less. 

  • 0 in reply to Sachin H K
    Prodigy 10 points

    Thank you very much for your reply. Here are the details you asked for:

    Are you operating in 32 channel mode or 16 channel mode ?

    We are operating in 32 channel mode.

    Do you mean System clock is 30MSPS ?

    No, I mean 30MSPS is the ADC Sampling Rate in 14-bit mode. The maximum ADC conversion Rate is 65MSPS in 14-Bit mode, but when working in 32 inputs mode the Sampling Rate is 0.5X of the ADC Conversion rate, therefore the maximum available sampling rate is 32.5 MSPS. We will operate slightly lower, at a Sampling Rate of 30MSPS.

    Also can you share the details of your sensor .

    The sensor type is not relevant here. There is an analog chain between the sensor and the ADC input (signal conditioning, gain stage, antialiasing filter, etc.). What I can tell you though is that there is a 3rd order LPF filter before the ADC with a 3MHz cutoff @3dB. So Nyquist is not the issue here, we just want enough samples from the input signal, hence the 30MSPS ADC Conversion rate.

    It all comes down to selecting the proper opamp to be used as the ADC driver. The signal connecting to the ADC driver is SE (Single Ended), we need to convert it to differential, this is why we were looking at the THS45x family.

    In order to do that, we need to start our calculations for:

    • The RC time constant of the kickback filter (the Rfilt and Cfilt between the driver and the ADC input)
    • The minimum required GBW for the driving opamp

    We already have the Csampling values and the detailed diagram of the input stage of the ADS52J90 from the datasheet, but to complete the calculations of the RC time constant and the values for the flywheel cap and the isolation resistor we need the value of the acquisition time (tacq). 

    With the sampling rate of 30MSPS we get a sampling period of 33.3ns, so I estimated the value of the acquisition time is going to be in the range of 20ns to 30ns, the rest being the conversion time. Still, going from 20ns to 30ns makes quite a difference in terms of minimum GBW for the driver opamp. Our goal is to select a driver with the lowest possible quiescent current, and flipping from say a driver with GBW of 250MHz to a GBW 450MHz makes quite a difference in terms of what is available and the Iq per driver. Would you be able to provide us with the tacq value when sampling at a rate of 30MSPS in 32 inputs mode?

    Thank you!

  • +1 in reply to Vlad Ardelean
    TI__Expert 7725 points

    Hi,

    In 32 ch mode if your FS is 60MHZ , then each input is will be converted at 30MSPS . tacq will be  16.6 ns(1/60e6) and conversion time will be 16.6ns (1/60e6). 

    So choosing amplifier bandiwth depends on how much settling you need . By rough calculation if you need 6T settling.. 6T = tacq.. In the above case T becomes 2.76ns . And 1/T is the bandiwdth required for opamp .In this case it will become 362MHz. 

    For further support on selection of opamp it is better to reach out opamp team as we dont have expertise in opamp.

    Hope this clarifies your query.

  • +1 in reply to Sachin H K
    Prodigy 10 points

    Hi Sachin, 

    To be honest, I did not expect the acquisition time to be equal to the conversion time. Most ADCs I worked with have shorter tconv than tacq to allow for more time for the input to settle.

    The functional block diagram in the data sheet (Page 28, Fig. 55) shows two independent clock triggers, one for sampling and one for conversion. If it's the same clock used for both, perhaps with the phase flipped, one would think the block diagram would show that, to make it clear that the sampling time and conversion times are equal...

    In any case, thanks again for your advice! I will use the tacq= tconv =  1/FS in 32 channels mode, which in my case is 16.66ns, for all subsequent calculations.

    All the best!