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ADS127L18: How to set DCLK frequency in Hardware Programming Mode

Ton Kuijper
Prodigy 90 points
Part Number: ADS127L18
Other Parts Discussed in Thread: ADS127L14

Tool/software:

Hello,

Datasheet says:

“The DCLK frequency is derived from the ADC clock through a programmable DCLK divider. See the Clock Operation section for details of the DCLK divider. Make sure the DCLK signal frequency is fast enough to transmit the channel data within one conversion period (FSYNC clock period), otherwise data are lost. Equation 22 shows how to derive the minimum required DCLK frequency.”

I want to use Hardware Programming so I have no access to any register. DCLK is an output so how do I set the DCLK divider?

I want to use daisy-chain over 1 line (DOUT0>DIN0) of 32 devices so I need many DCLK cycles. How do I get enough cycles to get all 256 channels out?

My output data will be 3 Bytes per channel only.

  • 0
    TI__Mastermind 47090 points

    Hello Ton,

    There is no way to set the DCLK divider in hardware control mode; it always defaults to a value of 1.  DCLK frequency will be equal to your clock frequency which will be limited to 32.768MHz typical in max-speed mode (33.6MHz maximum)

    The only option you have is to adjust the OSR setting, which also sets the output data rate.  Since you want 256 channels and 24b per channel, you need to transmit at least 24*256=6144b per conversion cycle, or, the DCLK frequency must be at least 6144*fDATA.  Also, fDATA=fCLK/(2*OSR), we can solve for the minimum OSR needed.

    fDCLK=fCLK

    fDCLK>Nb*Nc*fDATA

    Re-arranging:

    fDATA<fDCLK/(Nb*Nc)

    Nb=number of bits per channel=24

    Nc=number of channels=256

    fDATA=fDCLK/(2*OSR)=fDCLK/(Nb*Nc)

    OSR >= 0.5*Nb*Nc

    OSR >= 0.5*24*256

    OSR >= 3072

    You can use the Wideband filter or SINC4 filter with OSR=4096 or the SINC4+SINC1 with OSR equal to 3200, 6400, 12800, or 32000.

    Assuming fCLK=32.768MHz, your highest data rate using the Wideband or SINC4 filter will be 4ksps, and using the SINC4+SINC1 with OSR=3200, your maximum data rate will be 5.12ksps.

    If you need a higher data rate in your system, then you will need to reduce the number of channels in the daisy-chain and use multiple frame-sync ports on your processor or FPGA.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Prodigy 90 points

    Hello Keith,

    I think I digested your answer. Please confirm if I am correct. Daisy=chain 256 channels seems impossible for my settings.

     

    CLK=DCLK=2.097152 MHz, 64 ch x 24 bits= 1536 bits/conv, Low-Speed mode.

    fDATA

    OSR

    DCLK/Mbps

     

    Note

    256

    4096

    0.393216

     

     

    512

    2048

    0.786432

     

     

    1024

    1024

    1.572864

     

     

    2048

    512

    3.145728

     

    Not possible

    4096

    256

    6.291456

     

    Not possible

    8192

    128

    12.582912

     

    Not possible

    16384

    64

    25.165824

     

    Not possible

    32768

    32

    50.331648

     

    Not possible

     

    CLK=DCLK=8.388608 MHz, 64 ch x 24 bits= 1536 bits/conv, Mid-Speed mode.

    fDATA

    OSR

    DCLK/Mbps

     

    Note

    1024

    4096

    1.572864

     

     

    2048

    2048

    3.145728

     

     

    4096

    1024

    6.291456

     

     

    8192

    512

    12.582912

     

    Not possible

    16384

    256

    25.165824

     

    Not possible

    32768

    128

    50.331648

     

    Not possible

    65536

    64

    100.663296

     

    Not possible

    131072

    32

    201.326592

     

    Not possible

     Best regards,

    Ton

  • 0 in reply to Ton Kuijper
    TI__Mastermind 47090 points

    Hello Ton,

    Yes, if you reduce total number of channels to 64, then the above OSR settings and data rates are possible.

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    Prodigy 90 points

    Hello Keith,

    Thanks for your quick reply!

    In above (possible) data rates, the CLK is much higher than the bit rates on the output.

    There are much more DCLK pulses than needed to get all data out.

    Is DCLK stopping if all bits are shifted out? If not, what is on the output then?

    Best regards,

    Ton

  • 0 in reply to Ton Kuijper
    TI__Mastermind 47090 points

    Hi Ton,

    In daisy-chain mode, the data will continue to cycle through.  Since the ADC furthest from the controller does not have another ADC connected to its DIN pin, whatever this pin is set to will be clocked through all of the ADCs.  In the case of the below configuration, since DIN on the furthest ADC from the controller is connected to GND, then you will simply clock 0's until the beginning of the next frame.

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    Prodigy 90 points

    Thank you, Keith! That’s clear now.

     

    I want to get some higher fDATA and think of going to a 2-lane TDM as I understand 4-lane is impossible in hardware programming mode and for parallel output there is no output enable so for 64 devices I need to bring 512 lines to my FPGA which is impossible. But trying to use 2-lanes TDM I think I bump into some discrepancy in the datasheet.

     

    Table 7-16 (page 61) says:

    Data port TDM (pin 3):

    1= TDM mode, one data lane (DOUT1 pin).

    F= TDM mode, two data lanes (DOUT1 and DOUT2 pins).

     

    Figure 7-34. DP_TDM = 01b (One or Two DOUT Pins, Serial or Parallel)

    (chosen by making TDM pin 3 floating)

    The timing diagram shows 2 data lines, DOUT0 and DOUT1.

    While table 7-16 says something different: DOUT1 and DOUT2.

     

    Figure 7-35. DP_TDM = 00b (One DOUT Pin, Full Serial)

    (chosen by making TDM pin 3 a “1”).

    The timing diagram shows 1 data line, DOUT0.

    While table 7-16 says something different: DOUT1.

     

    Best regards,

    Ton

  • 0 in reply to Ton Kuijper
    TI__Mastermind 47090 points

    Hi Ton,

    Table 7-16 is incorrect; thanks for catching this error.  We will correct this on the next datasheet revision.

    Figures 7-34 and 7-35 are correct.

    Table 7-16 should read as follows:

    Data port TDM (pin 3)

    0= No TDM, four (ADS127L14) or eight (ADS127L18) data lanes (all DOUTn pins are used)

    1= TDM mode, one data lane (DOUT0 pin)

    F= TDM mode, two data lanes (DOUT0 and DOUT1 pins)

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    Prodigy 90 points

    Hello Keith,

    I have 2 questions:

    1. I change to one-lane (D0) serial mode (pin 3 HI) to get my data out and use a small FPGA on a board with 8x ADS127L18. The FPGA combines the 8 streams in one fast stream to the FPGA on my main board.

    Can I leave data-lines D[7:1] open or should I terminate them?

    2. Why is the datasheet of the ADS127L18 removed from the TI website? I hope not because the design is withdrawn???

    Best regards,

    Ton

  • 0 in reply to Ton Kuijper
    TI__Mastermind 47090 points

    Hi Ton,

    DOUT1 is always an output, and should be left floating.  All other DOUT pins DOUT[7:2] default as inputs, and can be used as GPIO pins.  You can connect these pins to ground, or use pull-up/pull-down resistors if you want the option to use these as GPIO at some later time.

    We are getting ready to release the part.  Normally, the website only goes down for a few hours to transition from the preliminary product folder to the released (Active) folder with updated datasheets.  Unfortunately, we had a 'glitch' and the preliminary product folder was taken down too soon.  Do not worry, this product will be fully released within the next several days and you will be able to order production (Active) devices at that time.

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    Prodigy 90 points

    Thanks again for your fast reply Keith!

    Since I use hardware programming mode, I understand I cannot use the GPIO because I cannot get the data out ?

    So if I use DOUT[0] as a serial output I must leave DOUT[1] unconnected and MUST connect DOUT[7:2] to ground.

  • 0 in reply to Ton Kuijper
    TI__Mastermind 47090 points

    Hi Ton,

    That is correct.  I forgot you are using Hardware programming mode.  In either case (Hardware or SPI configuration), the DOUT1 pin should always be floating, and the remaining DOUT[7:2] should be connected directly to ground.

    Regards,
    Keith