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ADS42LB69: Sample synchronization across the two ADCs

Andrew Chen
Prodigy 10 points
Part Number: ADS42LB69


Tool/software:

I have two ADS42LB69s fed by the same clocks. ADCs are controlled by an FPGA. SYNCINs are not used. I am "calibrating" clock and data alignment of each ADCs using IDELAYs and test patterns. However, I noticed that the two ADCs samples could be off by +/-1 samples when comparing data across the two ADS42LB69s. Would love some ideas on how to synchronize samples. 

  • 0
    TI__Mastermind 39980 points

    Hi Andrew,

    Are all the clocks to the ADC and FPGA the same length?

    How about the analog inputs to each ADC? Are those circuits the same and length matched?

    Regards,

    Rob

  • 0
    Prodigy 10 points

    Hi Rob, clocks to ADC and FPGA are off the same length. Analog inputs to each ADC are also length matched. I am looking at some of the timing information. Looks like Tpd has a window of 7-13 ns. With sampling rate of 250 MHz, the maximum could be up to 5ns. 

  • 0 in reply to Andrew Chen
    TI__Mastermind 39980 points

    Hi Andrew,

    Thanks for the additional information. I am checking with design on this.

    Please give me a few days to respond.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    TI__Mastermind 39980 points

    Hi Andrew,

    We looked into this, and the specification is a bit mis-leading.

    The range of the Tpd covers all voltage and temp conditions, a spread like this from part to part is not likely and not what they can expect.

    I assume you are just asking? Have you implemented this into your system and seeing this effect? Can you please confirm?

    if this has been implemented, can you double-check the polarities on the frame & data clocks?

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 10 points

    Thanks Rob, we implemented this ADC into a design already. That is when we noticed samples can be off by +/- 1. But we do not have the frame clocks routed to FPGA currently. I am studying if routing frame clocks would be good enough to keep them in sync. Are you thinking the frame and data clocks from one unit to the next would be in sync if we use the same input clock source (division by 1)? 

  • 0 in reply to Andrew Chen
    TI__Mastermind 39980 points

    Hi Andrew,

    Yes, you would need to route all frame and data clocks from each ADC device to the FPGA in order to sync appropriately. Otherwise, there can be some variance. The data lines should be the same length as well.

    If you can forward some schematics or a block diagram on what has been implemented that would help us provide more guidance.

    Thanks,

    Rob