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DAC3484: DAC3484 initial fail

yu wu
Prodigy 20 points
Part Number: DAC3484


Tool/software:

Hi, Sir,

            Can I use DAC3484 as simple DAC converter? we follow power up sequence(from datasheet), after RESETB toggle, we start configure register,

I disabled QMC,NCO,Interpolation filter and PLL, But when I check config05 register, I found that bit10, bit6 and bit5 always keep 1. that means “DACCLK has been stopped”， "reserved" and "PLL lost lock"

when we change input LVDS signal, trying to adjust IOUT, but IOUT always keep same value, can't control. can you help to told us which how to deal with it? many thanks!

  • 0
    TI__Guru* 79294 points

    Hi,

    Yes, you can use the DAC3484 without additional digital features. Please refer to section 7.5 for example configuration, and you can disable un-used digital logics.

    DACCLK has stopped means that there are no DAC sampling clock present. Please check the LPVECL level clock from your clock generator. This is the first step to get the DAC3484 working.

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 20 points

    Hi, Sir, from signal measurement, DACCLK always working and have good signal quality. But we are using FPGA+DAC3484, FPGA LVDS output transform to LVPECL by AC couple. refer 

    TIDA-00077, can you help to confirm it is OK? or we should use DC couple?

  • 0 in reply to yu wu
    TI__Guru* 79294 points

    Hi, 

    If you are not using the on-chip PLL, then the on-chip PLL alarm is expected to be logic HI. The on-chip PLL alarm will only clear if the on-chip PLL mode is used and the PLL is configured correctly.

    If DATACLK and DACCLK do not have phase locked or phase aligned, then it is possible to observe DACCLK_GONE issue as the rate of counting DATACLK or DACCLK has mismatch. 

    -Kang