This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC3562: SCLK between Register Adress and Register Data

Part Number: ADC3562

Tool/software:

Hello team,

Customer wants to put pause to SCLK after last clock of Register Address bit, as shown on the diagram below.

How long can it wait after falling edge of register address?

Best Regards,
Kei Kuwahara