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ADC3910D065: Programming eval board

Jonathan Kolbrak
Intellectual 500 points
Part Number: ADC3910D065
Other Parts Discussed in Thread: ADC3910D125EVM, TSW1418EVM,

Tool/software:

Trying to load the FPGA for the capture card and get these errors:

"Enable end of startup check" Box checked:  

ERROR: [Labtools 27-3165] End of startup status: LOW
ERROR: [Common 17-39] 'program_hw_devices' failed due to earlier errors.
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210249BAC1C1

or

"Enable end of startup check"  Box unchecked:

ERROR: [Labtools 27-2312] Device xc7a100t_0 is no longer available.
Check cable connectivity and that the target board is powered up then
use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target.
Use open_hw_target to re-register the hardware device.
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210249BAC1C1

Then a power cycle of the card is required but still has this error.

Using Vivado 2022.2

Thanks,

Jon

 

  • 0
    TI__Intellectual 1370 points

    Hi Jon,

    You can see this error if Vivado detects that the JTAG dongle has lost connection to the FPGA, or the FPGA has lost power during programming. Please ensure that everything is connected according to the user's guide: both the EVMs have power, both EVMs have a usb connection, and all jumpers are configured properly on the TSW1418EVM according to the ADC3910D125EVM user's guide. If everytrhing is set up properly, you could have a bad USB cable, or you could be connected to a USB port that is not capable of supplying enough power for the FPGA. If you are using a USB Hub for the TSW1418EVM USB or JTAG Dongle USB connections, try connecting directly to the PC. Try swapping out the USB cables and the USB ports you are connecting to for these connections.

    Best,

    Luke

  • 0 in reply to Luke Allen
    Intellectual 500 points

    Hi Luke,

    I was able to figure out that the USB and Digilent JTAG pod were conflicting.  So I was able to program by removing the USB.

    Now however, when I program the FPGA using the supplied 10b_DDR.bit and .ltx files I get the following errors.:

    WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
    WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
    INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
    WARNING: [Labtools 27-3361] The debug hub core was not detected.
    Resolution:
    1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
    2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
    For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
    WARNING: [Labtools 27-3413] Dropping logic core with cellname:'design_1_i/DCLK_ILA' at location 'uuid_9E5F81CB5AFE5EBD9B083A60DFA7040F' from probes file, since it cannot be found on the programmed device.
    WARNING: [Labtools 27-3413] Dropping logic core with cellname:'design_1_i/DCLKz_ILA' at location 'uuid_D4760B86CACE5B4A85361056704FD62B' from probes file, since it cannot be found on the programmed device.

  • 0 in reply to Jonathan Kolbrak
    TI__Intellectual 1370 points

    Hi Jon,

    Glad to hear you are able to program now. These warnings typically occur when the FPGA design does not detect a DCLK from the ADC. There are a few things that could be causing this. The DCLK is genrated by the ADC from the sample clock. Assuming you are providing a 65MHz clock signal (since you are using the ADC3910D065) to the SMA connector on the EVM labeled CLK, ensure the clock amplitude is sufficient, around 10dB. You also need to ensure that you program the ADC by running the ADC3910D125EVM_API_Rev0.1.py python script provided in the software package. The ADC will not output a DCLK until it has been programmed using this script. Therefore, you must provide a CLK, run the script to program the ADC, then program the FPGA in that order. This sequence should allow you to program the FPGA and capture data. If you are still recieving errors, please let me know and we can set up a call to debug your setup.

    Best,

    Luke