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AFE58JD48: AFE58JD48 configuration

Wenping Wang
Prodigy 30 points

Part Number: AFE58JD48

Tool/software:

I hope to configure the AFE with FPGA and establish a high-speed interface using the JESD204B protocol (subclass 0/1/2). The AFE uses the 40x mode, and the correctness of SPI read and write has been verified.

The configured registers are as follows:

SPI_DIG_EN = 1 00_0001 # Global reset and self-clearing.

SPI_DIG_EN = 1 C5_4000 # According to "12.2 Device Initialization".
SPI_DIG_EN = 1 D0_0001 #
SPI_DIG_EN = 1 DE_00C3 #
SPI_DIG_EN = 1 DF_0040 #
SPI_DIG_EN = 1 1E_0003 #
SPI_DIG_EN = 1 12_0005 #
SPI_DIG_EN = 1 2A_0800 #
SPI_DIG_EN = 1 12_0000 #
SPI_DIG_EN = 1 11_FFFF #
SPI_DIG_EN = 1 25_0002 #
SPI_DIG_EN = 1 11_0000 #
SPI_DIG_EN = 1 12_000a # JESD 40X mode.
SPI_DIG_EN = 1 12_000A.
SPI_DIG_EN = 1 31_02C0.
SPI_DIG_EN = 1 34_0907.
SPI_DIG_EN = 1 35_03C0.
SPI_DIG_EN = 1 36_0007.
SPI_DIG_EN = 1 12_0000.

The FPGA uses the Vivado IP JESD204B RX. The configuration parameters are a 5G line rate, F = 4, and K = 8. The sysref frequency is 7.8125 MHz.

After configuration is completed, sync can be pulled high, but it will be repeatedly pulled low and then re-establish the link. When checking with software before sync is pulled low, the AFE sends 0xbc. After sync is pulled high, the data received by the FPGA is repeated data.

My question is whether there is a problem with the configuration of the FPGA or AFE that causes sync to be pulled low. Why is the data received after sync is pulled high a repeated fixed number instead of a random number?