Tool/software:
We are using the ADS4128IRGZT ADC from TI in one of our projects.
The ADS4128IRGZT has a clock input and a clock output. Data output of this ADC is in sync with the clock output.
We feed a 100MHz clock to the ADC generated by a clock wizard inside an AMD Artix 7 FPGA. The data output of the ADC is captured by the FPGA using the ADC clock output signal.
I have Implemented an Integrated logic Analyser (ILA) Inside the FPGA, capturing the various clocks for the ADC and the Data output bus of the ADC.
We are using the ADS4128IRGZT ADC configured for CMOS output with two’s complement.
Below there is a screenshot of the FPGA ILA showing the clocks going and coming from the ADC
The ILA clock is 400MHz again generated inside the FPGA. Signal “adc_clk” is the 100MHz clock generated by the FPGA and FED to the ADC. Signal “sample_clk” is the clock output from the ADC.
It seems like the ADC varies the duration of the clock high pulse as you can see from the screenshot. Is this how the ADS4128IRGZT ADC works? Does it vary the high level of its clock output to in relevance to its conversion time? Something like this is not mentioned in the Datasheet.
There are occasions that it misses clock pulses as well.
Another issue is the following:
The ADS4128IRGZT ADC has another clock input for its serial configuration interface. I have opted to interface the serial interface with the FPGA as well and drive it with a 6.25MHz clock (transmitter_clk in the screenshots)
The Datasheet specifies this serial interface clock between 1 and 20MHz.
A weir phenomenon occurs when both the serial interface clock and the 100MHz clock are fed to the ADC. The clock output of the ADC then seems to produce a somehow “combined clock” as you can see form the screenshot below.
Let us know if you can or cannot help with the issues above.
