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ADS9218: Table 6-7 Register Map Settings vs Fig 7-15 & Fig 7-40 seem to disagree.

Jim Overbeck
Prodigy 20 points
Part Number: ADS9218
Other Parts Discussed in Thread: ADS9219,

Tool/software:

This application requires an ADS 9218 with SMPL_CLK = 8 Mhz.  It should be set up to have 24 bit data frame, SDR, with one output lane and decimation of 2.  Fig 7-15 recommends setting DATA_LANES to 7 for one output lane and 24 bit data.  Fig 7-40 recommends setting CLK1 = 1 for DATA_LANES = 7.  That setting disagrees with Table 6-7 24 bit, SDR, 1 Output Lane -- that row shows CLK1 = 0.  Which is correct?

  • 0
    TI__Expert 4980 points

    Hello Jim, 

    Thank you for bringing this up, Table 6-7 will need some changes as well as additional clarification. Apologies for the confusion. 

    I would follow Figures 7-15, 7-40, as well as Table 6-8.  . The ADS9218 and ADS9219 do not support SDR nor 1-lane if averaging is not enabled. 

    Table 6-7 does not include the averaging requirement and would also need some updates to reflect that and match Table 6-8 as well.   I will submit a report to update this on the next datasheet revision. 

    I hope this helped, please let me know if additional clarification or any other help is needed. 

    Best regards, 

    Yolanda 

  • 0 in reply to Yolanda Gonzalez
    Prodigy 20 points

    Hi Yolanda,  I will disregard Table 6-7.  I noted one more disagreement, if you're updating that table.  Register C5h "CLK3" should be set to 1 for DATA_LANES = 7, Table 6-7 shows 0.  I do have averaging on with decimation set to 2.  Thanks! Jim

  • 0 in reply to Jim Overbeck
    TI__Expert 4980 points

    Thank you Jim! 

    I will add that into the updates! Thanks as well for being understanding! 

    Best regards, 

    Yolanda