ADS7066: Setting up SPI communication library

Hello Sumayyah! Welcome to the TI E2E Forum!

Thank you for your question! If you are new to SPI protocol I would also suggest watching one of our Precision Labs Videos/Trainings, we have an SPI Communications Basics, that could be helpful.  

I apologize for the delay, I was traveling and was unable to respond sooner.

To cover some SPI basics that are available for the ADS7066

                SPI Configuration:

SPI typically is a 4-wire system, it needs a Clock (SCLK), Chip-Select (CS), SDI (Serial Data In), and SDO (Serial Data Out).   There are some devices that can work with slightly different configurations like 3-wire, enhance, etc. but for the ADS7066 we will just use the 4-wire.   The communication between devices using SPI is usually split in frames, a CS toggle will start the frame and another end it. During that frame the SCLK should have enough clock periods to send/receive the complete data packet. For the ADS7066 it will typically be 24 clocks (there are some modes that will require a different amount but those will be noted. 

*One important thing to consider is to make sure that the Host (Controller used to communicate to the ADS7066) and the Peripheral (ADS7066) are connected correctly. The controller will typically have or be configurable to have the same 4-wire SPI lines. What needs to be confirmed here is that the lanes match, SCLK should go to SCLK, CS to CS, but for SDI and SDO it would be the other way around. Since the controller is outputting data to control the peripheral the SDO of the controller should be connected to the SDI of the ADS7066. Inversely for the SDI, the controller will be reading data from the ADS7066, so the controllers SDI should be connected to the ADS7066’s SDO.                

                SPI Protocols

                There are typically 3 variables to consider for SPI to ensure the data is transmitted and received correctly by both the host (Controller) and the Peripheral (for this case the ADS7066). There is a Clock Polarity (CPOL), and Clock Phase (CPHA) and CS. The Clock polarity designates if the SCLK starts Low (CPOL = 0) and toggles or if it starts High (CPOL = 1) and then toggles. The Clock Phase (CPHA) designates if the data will be read on the Leading Edge (Rising Edge if CPOL = 0 or Falling Edge if CPOL = 1) of the SCLK (CPHA =0) or the Following Edge (Falling Edge if CPOL = 0 or Rising Edge if CPOL = 1) of the SCLK (CPHA =1). For Chip Select what needs to be considered is if it’s a High Trigger or Low trigger, typically this is shown by if there is a Bar on top of the CS, if not CS is trigger high, meaning it starts low and it goes high when SPI communication begins. More commonly the   will have a bar meaning it is trigger low, so the CS will start high then go low when the communication begins. These configurations need to be set and match for both the controller and the ADS7066.  

Some more specific ADS766 SPI communication things to consider are:

                Writing to a Register

                Most ADC have a Register Map that can be used to configure the device indifferent modes. This map can usually be found towards the end of the end of the datasheet. The register map usually has multiple registers, each with a different address and default/reset/offset value (this will be shown in the register map), register sizes are usually device specific, for the ADS7066, each register is 8 bits long.  Within each register there are usually multiple configurations found, the size of each configuration can be anywhere from 1 bit to the full registers (8 bits).

                To write to a register there is a specific format to follow shown below:

                The first 8 bits will be to enable a write register action, the next 8 bits are for the register address and the last 8 bits are to configure the registers.

                Reading from a Register

                Reading from a register will take 2 frames, the 1^st will be to let the device you want to read from it and the 2^nd will be to read the data from the SDO.

                In the 2^nd frame it could either be all 00s or it can be an additional command (register read/write).

                Reading ADC Data

                Typically writing a NOP (all 0s) on SPI will output the ADC data of the last configured ADC channel on SDO. This device has multiple channels and options to configure each channel and mode of data collection. The channels can either be Analog inputs of General Purpose Input/Outputs (GPIO), the data collection mode can either be Manual, Auto-Sequence, or On-the-Fly. Please read the datasheet for more information on this. The general idea is that the channel you wish to read from should be configured 1^st, then a following NOP command will output the ADC data on the SDO (some mode will require you to wait 2 frames to get the data on SDO, but that would be noted within the explanation of the mode).

                Sample Code

It is providing is a basic format that takes care of configuring all that was mentioned above

“ads7066.h” is a header file with the register map, which makes it easier to write to specific configurations within each register instead of the full register each time.

Within “ads7066.c” is where the bulk of the configuration/usability is at.  And the commands are named to make it more intuitive, like “readData”, “readSingleRegsiter”, “writeSingleRegister”, “setRegisterBits”. “initADS7066”, “startManualConversions”, etc.

Please let me know if you have more specific questions for the SPI, device configuration, or the example code.

Best regards,

Yolanda