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ADC31JB68: JESD204B FPGA IP: TI204C-IP

Part Number: ADC31JB68

Tool/software:

I requested this IP through the website to use with this ADC, still listed as pending. Is that IP still available?

  • Hi Mark,

    Please give a couple of days for the request to process. Then you should receive an email with a request form and we will be able to grant you access once this form is completed. 

    Regards,

    David Chaparro 

  • Hi David,

    I'm filling out the Excel sheet for this. I am having difficulty completing the ADC tab (I'm also referencing your slap161 document):

    Fs [GSPS]: is this the sampling rate of the ADC alone?

    - Decimation: is this the case for an ADC with a built in DDC? Since the ADC31JB68 does not have that, this becomes 1?

    - Data Rate [MSPS]: is this the actual data rate out of the ADC JESD204 ports?

    - LMFS or JESD mode: this one confuses me - are these not the same? Or is this asking if we are using the lanes alone or with added control signals like SYSREF or ~SYNC, basically asking what subcalss we are using?

    - Lane Rate [GSPS]: how is this different the Data Rate above?