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ADS9218: When is the internal S/H circuit sampling the input vs holding the value and converting it?

Jim Overbeck
Prodigy 20 points
Part Number: ADS9218

Tool/software:

We're using a sample hold circuit ahead of the 9218 and then performing 2 conversions and averaging the result.  Is there a timing diagram that notes when the A/D is sampling it's input so I can assure that my input signal is in a valid state?  In the diagram below the green trace is the raw signal, the red line is the output of my S/H and ideally, I'd like to align the ADS9218 to sample at the red x marks.

  • 0
    TI__Intellectual 1630 points

    Hello Jim,

    Welcome to the TI Forum, and thank you for your question! Apologies for the delay due to the weekend. 

    For the ADS9218 family of the devices, the falling edge of the sampling clock is what starts the sampling of the of the ADC. It would be recommended to ensure the input to the ADS9218 is in its valid state at least marginally before that. 

    If I may ask, is the ADS9218 being used for an imaging application? 

    Best regards, 

    Yolanda 

  • 0 in reply to Yolanda Gonzalez
    Prodigy 20 points

    Thanks Yolanda.  While the raw input looks like video, it's not an imaging application.