TSC2007: I2C pin level at POR

dai_sakamoto

Part Number: TSC2007

Tool/software:

When the Vdd pin is set to 0V during POR,

do the SCL and SDA pins need to follow Vdd?

The datasheet says "Digital input voltage to GND" -0.3V ~ Vcc+0.3V But the POR application documentation doesn't seem to follow that.

Which one is correct?

datasheet↓

Important Considerations to Assure a Safe POR↓

6 days ago

0 dai_sakamoto 6 days ago

Prodigy 180 points

What I would like to know is, does the pull-up power supply have to be the same as Vdd?

+1 Daveon Douglas 5 days ago in reply to dai_sakamoto

TI__Mastermind 18750 points

Hi Sakamoto,

Those are the absolute maximum voltage ratings the digital input and output pins can withstand before damage could occur.

The POR timing diagram is correct, SCL and SDA should be stable high before PENIRQ.

Digital pins (SCL/SDA/PENIRQ, etc.) are typically pulled up to VDD sharing the same supply, but if the application uses a separate rail there should be no concerns

0 dai_sakamoto 5 days ago in reply to Daveon Douglas

Prodigy 180 points

Thank you.
Just to confirm, is it correct that the IC will not break down even in the case of the circuit and waveform shown below?

+1 Daveon Douglas 4 days ago in reply to dai_sakamoto

TI__Mastermind 18750 points

Hi,

I dont see any concern using the FETs to act as a switch for VDD supply to control the power sequence. I would recommend a larger decoupling cap, maybe 1uF, on VDD to improve power stability.

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TSC2007: I2C pin level at POR