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ADS1291: nRESET transition rate

Nate Morrison
Prodigy 30 points
Part Number: ADS1291


Tool/software:

I would like to know if there are any restrictions on the nRESET signal transition rate.  We'd like to apply an RC filter to this input to help clean up some interference picked up on an interconnect.

The datasheet is not clear about this.  According to Fig 72 and Table 29, the reset pulse width needs to be more than 1 tmod (about 8us for internal clock).  Our design meets that.  It does not state anything about the rate of change.  An RC filter would provide a slower edge to this signal than a logic gate for example. 

What limit should I apply for transition rate?

  • +1
    TI__Guru 66896 points

    Hi Nate,

    Thank you for your post.

    We do not have strict rise/fall time requirements on any digital I/O signals in the ADS129x family as the SPI transactions generally occur at relatively low speeds. For nRESET, all that is required is that the low logic low voltage threshold be satisfied for at least one modulator clock cycle, such that it can be read and latched on the next clock edge. I would think adding an RC to this pin would be fine, so long as the I/O logic thresholds are met for the minimum duration. Adding some margin to the nRESET low time will not hurt.

    When the device comes out of reset, an excessively slow rising edge on nRESET will make it less clear when to begin counting the 18*tCLK delay before using the device. Adding some margin here should be good enough to ensure the device is ready for communication following a pin reset.

    Regards,

    Ryan