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ADS62C15: Looking for ADC and DAC with high sampling rate

Long Le
Prodigy 60 points

Part Number: ADS62C15
Other Parts Discussed in Thread: DAC5672, , ADC3422, ADC3224, ADC3644

Tool/software:

Hi TI supporter,

I am looking for the ADC 125 Msps include 2 channel /chip with parallel interface (at least 12 bits). And the DAC up to 250 Msps with parallel interface (at least 12 bits)

I saw the ADS62C15 and DAC5672 seem to meet the requirement but have some question below:
1. I saw the ADS62C15 named " serial LVDS" interface. Can you help to explain the different between parallel cmos interface vs Serial LVDS.
2. The ADS62C15 only have 11 bits resolution in description, but the block diagram show 14bits. Can you refer the others have 12 bits and lower price also.
3. Can you suggest the FPGA/ MCU for using x4 DAC and x4 ADC with CMOS parallel interfacing.
4. Please provide some evb schematic related to DAC/ ADC with parallel cmos interface to FPGA/MCU

Thank you,
Long Le

  • 0
    TI__Prodigy 690 points

    Hi Long,

    I would recommend you take a look at ADC3644 (14b, 2ch, 125MSPS, DDR CMOS) as our newest ADC option. If you want a lower cost 12-bit then take a look at ADC3224 (12b, 2ch, 125MSPS, Serial LVDS). If you need more ADC channels, then there is the ADC3422 which is a quad channel ADC.

    The timing diagrams of each ADC will give you an idea of the difference between Parallel CMOS and Serial LVDS interface. CMOS is a slower interface compared to LVDS, so you need more pins to transmit the same amount of data. ADC3644's CMOS interface uses 7 lanes per channel to output 2 bits per clock cycle (1 bit each on rising and falling edge) while ADC3224's LVDS interface outputs 12 bits per clock cycle.

    Depending on which interface you use will determine the FPGA you can use based on lane rates and number of pins.

    The ADC3644EVM is available on the product page with design files. You can interface the board with the TSWDC155EVM data capture board.

  • 0 in reply to Dalton Stringer
    Prodigy 60 points

    Hi Dalton,

    So it means if I use the CMOS interface, the FPGA clock should be at least 125 Mhz; and if I using LVDS, the FPGA clock should be 125 x6 Mhz ?
    So with LVDS, we are facing with the FPGA speed?

    With the TSWDC155EVM, I can not see the design file for reference, just see the User Manual only.

    Thank you,
    Long Le 


  • +1 in reply to Long Le
    TI__Mastermind 45670 points

    Hi Long Le,

    Is the LVDS interface is serial, then yes, the FPGA clock or data clock will be a multiple of the sampling clock in order to capture the data correctly.

    This should be well specified in the ADC device's datasheet.

    Regards,

    Rob