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AFE5832LP: AFE_PDN_FAST

Philippe Rubbers
Prodigy 90 points
Part Number: AFE5832LP
Other Parts Discussed in Thread: TX7332

Tool/software:

I am not sure if I understand the AFE_PDN_FAST specifications

1) AFE_PDN_FAST requires 8us to wake up
2) but only if last woken up <500us previously, failing which it requires 4ms to power up.

What method is recommended to keep the device in partial power down (and not fully powered down)?
If a (-ve) pulse is sent every 500us for 18us?  or is a longer pulse required (and for how long)?

Our current operational sequence is as follows, but the automatic DC Offset indicates that the capacitors are still charging up after 18us  (8+8+2us).
1) -ve pulse the AFE_PDN_FAST (wake up)
2) wait 8us for wake up
3) TX_Trig (to synchronise AFE)
4) power up the TX (using TX7332) 
5) wait another 8us (for TX7332 to wake up)
6) pulse the TX7332
7) wait 2us for TX7332 to pulse and TR switch to activate
8) shut off power to TX7332.
8) start capturing on the AFE
9) end capturing
10) send  AFE_PDN_FAST (+ve) to put AFE back into power down.

process the data and send to imaging.... and repeat.
Our processing takes <200us, so meeting the 500us requirement, yet the automatic DC-offset is not yet settled (in the 16us between AFE_PDN_FAST=0 to start capturing).
Please advise.

  • 0
    TI__Expert 4631 points

    Hi,

    Can you clarify for how long will you be keeping device in fast power down mode before waking it up? The spec is, if device remains in power down mode for more than 500us then you will need to give longer time for device to wake up. If device is placed in power down state for less than 500us then device can wake up within 8us.

    Regards,

    Shabbir

  • 0 in reply to Shabbir Amjhera Wala
    Prodigy 90 points

    Hi Shabbir.
    Thanks for coming back to me.....
    typically around 200us. 
    The device has woken up within the 8us, but I see artefacts on the automatic DC correction.
    So the question is: what is the correct approach to use to minimize power consumption while eliminating DC correction artefacts.
    Specification states I require 4ms if >500us.... but this appears super conservative: 8us to 4ms appears quite a jump at the 500us boundary.

  • 0 in reply to Philippe Rubbers
    TI__Expert 4631 points

    Hi,

    What kind of DC artifacts are you seeing? If the DC settling issue is happening at 200us then increasing the power down time wont change the behavior.

    Regards,

    Shabbir

  • 0 in reply to Shabbir Amjhera Wala
    Prodigy 90 points

    I can see the capacitors recharging as per the image attached (extreme case).
    the more the number of active elements, the more obvious the artefacts.
    I am not proposing to increase the power down time (obviously I want to minimize this for improved performance).
    I want to minimize the power consumption (and minimize the artefacts)

  • 0 in reply to Philippe Rubbers
    TI__Expert 4631 points

    Hi,

    Thanks for details. But given offset variation looks very high. This is not expected performance from device. I would expect offset to settle within 10us. Also settled offset in your picture looks high. If you dont power down the device then what is settled offset do you see across chs?

    Regards,

    Shabbir 

  • 0 in reply to Shabbir Amjhera Wala
    Prodigy 90 points

    Hi Shabbir

    The problem is that the DC offset is not yet settled after 8us.
    The device wakes up in 8us, after which we can trigger it (TX_Trig).
    We must then wait for the DC offset number of points to be captured internally.
    We set this to 128 points (Reg 4, bit 12-9=0001: AUTO_OFFSET_REMOVAL_ACC_CYCLES[3:0]) to be as short as permissible.
    at 25MHz sampling rate (AFE clock at 50MHz as per the waveforms), we would then require 128*40ns=5.12us before we may trigger the TX.
    this should not be a limiting factor, as we have to wait 10us for the TX to charge up and pulse and TR switch to close.
    So this is 18us as per my first message.
    It is clear the DC offset requires more time to settle than the 8us switch-on time..... but it does not appear documented.
    Hence our request for further information on the AFE_PDN_FAST specifications.

    At full speed of 40MHz sampling rate = 80MHz AFE clock), using 128 points, the DC artefacts are mostly gone, and this is possibly the regime under which the document was drawn up..... at slower speeds such as 5MHz sampling rate (10MHz AFE clock), the 128 points takes 128*200ns=25.6us, and then this is sufficient time for the DC offset to be also mostly gone....so it is the intermediate speeds that are the issue.