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ADC09QJ800-Q1: Initialization

David Wende
Intellectual 740 points

Part Number: ADC09QJ800-Q1
Other Parts Discussed in Thread: ADC09QJ1300EVM

Tool/software:

Hello forum

I am using an Arria 10 FPGA as the receiver for this ADC.

The link is not working, and as far as I can tell the synchronization sequence is not completing (based on the fact that the SYNC_N signal remains low).

As a first step I would appreciate if TI could verify that the initialization sequence below is correct.

In addition, I have attached an excerpt of the relevant schematic.

The input clock to the ADC is LVDS 100MHZ. Note that the polling does succeed in steps 3, 16 and 17 below.

My desired sample F is 500MSPS.

Sequence I am using is:
1. Set Power On
2. Soft Reset (0x80 to 0x0)
3. Poll bit  0 in 0x270
4. CPLL Reset (1 to 0x5C)
5. VCO Bias (0x4A to 0x3F)
6. PLL (0x9 to 0x3D)
7. PLL (0x5 to 0x3E)
8. CPLL no reset (0 to 0x5C)
9. JESD EN (0 to 0x200)
10. CAL DIS (0 to 0x61)
11. JMODE (2 to 0x201)
12. KM1 (0x1F to 0x202)
13. Various (2 to 0x204)
14. Calibrate settings (1 to 0x62)
15. Calibrate settings (1 to 0x65)
16. POLL VCO CAL DONE, Poll bit 0 in 0x5E
17. POLL CPLL LOCKED, Poll bit 0 in 0x208
18. Enable CAL state machine (1 to 0x61)
19. Restart JESD (1 to 0x200)
20. Finished

Much thanks

David

  • 0
    TI__Expert 6590 points

    Hello David,

    Can you please report the status of the JESD_STATUS register this will help determine where the issue is. I see the CPLL is locking but I am wondering if there is maybe something else going wrong.

    Thanks,

    Eric

  • 0 in reply to Eric Kleckner
    Intellectual 740 points

    Hi Eric,

    I will do this and send you the JESD_STATUS contents, but will take some days to get the setup working again.

    Please be patient.

    Thanks

    David

  • 0 in reply to David Wende
    Intellectual 740 points

    Hi Eric

    The value I am reading from 0x208 at the end of the sequence is 0x1

    i.e. only bit 0 is set.

    Thanks

    David

  • 0 in reply to David Wende
    TI__Expert 6590 points

    Hi David,

    I think I see another potential problem in your setup, after you are doing an ADC reset the init bit of the ADC does not seem to be reading back "1" which would indicate that the part completed all of its initialization process. See reg description below. This issue could be caused by the device not receiving a clock to run off. In your schematic I can see that you are driving the clock differential but I cant tell what the source of this clock is, is it an on board oscillator? If so can you please probe this input to the ADC and confirm that the clock signal is there.

    Thanks,

    Eric

  • 0 in reply to Eric Kleckner
    Intellectual 740 points

    Hi Eric,

    Why do you think the bit is not going to 1.

    In step 3 of the initialization sequence I am polling bit 0 of INIT_STATUS and this bit is going to 1.

    What could be the reason that bit 2  of 0x208 (JESD_STATUS) is not going to 1 at the end of the sequence, thus indicating that the SPLL is not locked?

    David

  • 0 in reply to David Wende
    TI__Expert 6590 points

    Hi David,

    Apologies I misread what your previous message was saying. The only reason that the SPLL is not locking would be that the ADC is not receiving a valid clock. Is the CPLL bit locking in the ADC JESD Status register? If so then this means the part is getting a stable clock using the cpll.

    Thanks,

    Eric

  • 0 in reply to Eric Kleckner
    Intellectual 740 points

    Hi Eric,

    Sorry the delayed response, I just returned this morning from an extended vacation.

    The CPLL locking bit is set, the SPLL lock bit is NOT set.

    How could this be?

    Did you ever manage to carefully check my initialization sequence that I sent in the first posting of this thread?

    Maybe I am making a mistake somewhere?

    David

  • 0 in reply to David Wende
    Intellectual 740 points

    Hi Eric

    We finally got the ADC09QJ1300EVM and copied the SPI sequence that the GUI sends to the board.

    I translated this to a TCL script and now both C-PLL and S-PLL are locking on our custom board.

    This working sequence is different from that mentioned in the data sheet.

    Could you comment on this?

    In addition, I would be very grateful if you could look at another thread of mine regarding this ADC.

    Thread ADC eval board

    Thanks

    David

  • 0 in reply to David Wende
    TI__Expert 6590 points

    Hi David,

    Can you share the exact writes you are writing to the ADC. Does it match what is shown above?

    Thanks,

    Eric