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TI-JESD204-IP: Vivado 2024.1 Synthesis of TI-JESD204-IP crashes with EXCEPTION_ACCESS_VIOLATION

aak
Prodigy 100 points
Part Number: TI-JESD204-IP


Tool/software:

Hi, 

When trying to syntheszie the IP core in Vivado 2024.1 I get the follow error

Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
Please check '...synth_1/hs_err_pid43636.log' for details

The error log unfortunately does not provide any more information.

#
# An unexpected error has occurred (EXCEPTION_ACCESS_VIOLATION)
#
Stack:
no stack trace available, please use hs_err_<pid>.dmp instead.

What might be the problem??

Thank you!

  • 0
    Prodigy 100 points

    I tried to disable incremental synthesis according an older post about this without it resolving the problem.

  • 0
    Prodigy 100 points

    Same issue in Vivado 2024.2

    Any suggestions would be appreciated. 

  • 0
    Prodigy 100 points

    We wish to interface to a TI DDS39RF0 in JMODE6, 1 Lane, 2 channels, 4 streams.

    Does the following generic map of the IP generate violate some restrictions that make it crash in synthesis??

    generic map (
      IP_ID => 0,
      -- IP type and protocol
      IP_TYPE => "TX",
      IP_PROTOCOL => 6466,

      -- Resolutions of the converter
      DAC_RES => 16,

      -- MGT Transceiver related parameters
      GT_TYPE => "GTHP",
      NUM_REFCLK_BUFFERS => 1,
      NUM_QUADS => 1,
      NUM_TX_LANES => 1,
      TX_LN_IDX_WIDTH => 1,
      TX_LN_DATA_WIDTH => 64,
      GT_USERIO_IN_WIDTH => 16,
      GT_USERIO_OUT_WIDTH => 16,

      -- 64b/66b protocol related parameters
      PARAM_TX_S => 1,
      PARAM_TX_E => 1

    )

  • 0
    Prodigy 100 points

    So it seems that the EXCEPTION_ACCESS_VIOLATION only happens when I instatiate the IP in a VHDL wrapper. If I use a SystemVerilog Wrapper the problem goes away.

    Now I'm getting other synthesis errors, but they are not related to what I have been seeing I suppose. Closing this for now.