AFE58JD48EVM: AFE58JD48EVM: Insertion loss of the SerDes traces from ADC digital output to FMC Connector

LALIT VERMA

Expert 1675 points

Part Number: AFE58JD48EVM
Other Parts Discussed in Thread: AFE58JD48,

Tool/software:

Hi Team,

We are planning to use this EVM with our board for JESD204B testing.

Now, our customer asking for the insertion loss budget of the complete link.

Please help in sharing the total insertion loss of all the 8 JESD SerDes lanes as below:

AFE58JD48 JESD Outputs -> PCB Traces -> AC Coupling Caps -> PCB Traces -> FMC.

This will help us in calculating the total channel loss of the link.

Thanks,

Lalit

0 Sachin H K 20 days ago

Hi,

Currently we don't have this data . Let me check once whether we have measured something similar before so that we can estimate for this .

0 LALIT VERMA 4 days ago in reply to Sachin H K

Expert 1675 points

Hi Sachin,

Any update on this.

Thanks,

Lalit

0 Sachin H K 1 day ago in reply to LALIT VERMA

Hi Lalit ,

If I understand correctly you want to use AFE58JD48EVM with your FPGA card for evaluation . What is the limitation of using TSW14J50 capture card ?

Below is the routing guidelines .

We are using FR4 material in the EVM. So based on this you should calculate the insertion loss for FR4 material .

Also for connector you should look online about what is the insertion loss.

In datasheet the eye diagram is given for 5GBPS and 10 GBPS .

Other customers are designing their board with FR4 with JESD length of 6-8 inch without any issue.

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