Tool/software:
What is the recommended approach for allowing the PD inputs (pin and etch) to have ground plan underneath?
In our application, the layout space is very tight (approx 4.4mm x 3 mm), slightly bigger than the part itself! With that said,
it's very difficult to keep the TX lines away from the PD input pins and etch. In fact, there are parallel runs where
the PD etch and TX etch are only a thin dielectric (in a flex circuit) away from each other.
One idea was to add another Cu layer in the flex assembly, and make that layer GND so that the TX and RX etches are
separated by that GND plane.
In discussions with partners of ours, advice came otherwise. There was apparently some history of noise coupling from
that GND plane into the PD inputs.
I do see GND under PD etches on your eval board, but that same run of etch drops down a layer onto the GND plane!
Could you please advise? Adding another layer to our stackup is not preferred, but if necessary to keep noise off the
PD inputs we'll head in that direction.